comp

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity comp is
    port (
        A: in std_logic_vector (3 downto 0);
      B: in std_logic_vector (3 downto 0);
        AHB, AEB, ALB: out std_logic
   );
end comp;

architecture dataflow of comp is

begin

    AHB <= '1' when A > B else '0';

    AEB <= '1' when A = B else '0';

    ALB <= '1' when A < B else '0';

end dataflow;