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  1. // PIC18F4620 Configuration Bit Settings
  2.  
  3. // 'C' source line config statements
  4.  
  5. // CONFIG1H
  6.  
  7.  
  8.  
  9.  
  10.  
  11. #pragma config OSC = INTIO67    // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
  12. #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  13. #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
  14.  
  15. // CONFIG2L
  16. #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
  17. #pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
  18. #pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)
  19.  
  20. // CONFIG2H
  21. #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
  22. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
  23.  
  24. // CONFIG3H
  25. #pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
  26. #pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
  27. #pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
  28. #pragma config MCLRE = OFF      // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
  29.  
  30. // CONFIG4L
  31. #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
  32. #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
  33. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
  34.  
  35. // CONFIG5L
  36. #pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
  37. #pragma config CP1 = OFF        // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
  38. #pragma config CP2 = OFF        // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
  39. #pragma config CP3 = OFF        // Code Protection bit (Block 3 (00C000-00FFFFh) not code-protected)
  40.  
  41. // CONFIG5H
  42. #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
  43. #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
  44.  
  45. // CONFIG6L
  46. #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
  47. #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
  48. #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
  49. #pragma config WRT3 = OFF       // Write Protection bit (Block 3 (00C000-00FFFFh) not write-protected)
  50.  
  51. // CONFIG6H
  52. #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
  53. #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
  54. #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
  55.  
  56. // CONFIG7L
  57. #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
  58. #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
  59. #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
  60. #pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
  61.  
  62. // CONFIG7H
  63. #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
  64.  
  65. // #pragma config statements should precede project file includes.
  66. // Use project enums instead of #define for ON and OFF.
  67.  
  68. #define _XTAL_FREQ 8000000
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