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BinaryToDecimal

giuliascott14 Mar 25th, 2019 (edited) 78 Never
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  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.all;
  3. USE ieee.numeric_std.all;
  4.  
  5. ENTITY BinaryToDecimal IS
  6.  PORT (SW: IN UNSIGNED(3 DOWNTO 0);
  7.        HEX0, HEX1; OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
  8. END BinaryToDecimal;
  9. ARCHITECTURE Behavior of BinaryToDecimal IS
  10.  
  11. --COMPONENTS
  12. COMPONENT comparator
  13. PORT (V: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  14.         Z: OUT STD_LOGIC);
  15. END COMPONENT;
  16. COMPONENT mux_2to1
  17. PORT(X,Y,S: IN STD_LOGIC;
  18.     M: OUT STD_LOGIC);
  19. END COMPONENT;
  20. COMPONENT circuitB
  21. PORT (INPUT: IN STD_LOGIC;
  22.          HEX1: OUT STD_LOGIC_VECTOR(0 TO 6));
  23. END COMPONENT;
  24. COMPONENT SevenSegmentDecoder
  25. PORT (SW : IN STD_LOGIC_VECTOR(0 TO 2);
  26.         HEX0: OUT STD_LOGIC_VECTOR(0 TO 6));
  27. END COMPONENT;
  28. --add here circuitA component
  29.  
  30. --INTERNAL SIGNALS
  31. SIGNAL out_comp: STD_LOGIC;
  32. SIGNAL out_A: STD_LOGIC(2 DOWNTO 0);
  33. SIGNAL out_mux: STD_LOGIC(3 DOWNTO 0);
  34. SIGNAL in_mux: STD_LOGIC_VECTOR(3 DOWNTO 0);
  35. SIGNAL in_comp: STD_LOGIC_VECTOR(3 DOWNTO 0);
  36.  
  37. BEGIN
  38. --giving the inputs to multiplexers, circuitA, comparator
  39. in_mux<=STD_LOGIC_VECTOR(SW);
  40. in_comp <= STD_LOGIC_VECTOR(SW);
  41. COMP: comparator PORT MAP(x_comp,out_comp);
  42. CA: circuitA PORT MAP(SW(2 DOWNTO 0),uscitaA );
  43. MUX1:mux_2to1 PORT MAP(x_mux(3), '0', out_comp, out_mux(3));
  44. MUX2:mux_2to1 PORT MAP(x_mux(2), out_A(2), out_comp, out_mux(2));
  45. MUX3:mux_2to1 PORT MAP(x_mux(1), out_A(1), out_comp, out_mux(1));  
  46. MUX4:mux_2to1 PORT MAP(x_mux(0), out_A(0), out_comp, out_mux(0));
  47. CB: circuitB PORT MAP(out_comp,HEX1(0 TO 6));
  48. DEC: decoder PORT MAP(out_mux(3 DOWNTO 0), HEX0(0 TO 6));
  49. END structure;
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