tb_schematic.vhdl

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY schematic_schematic_sch_tb IS
END schematic_schematic_sch_tb;
ARCHITECTURE behavioral OF schematic_schematic_sch_tb IS

   COMPONENT schematic
   PORT(  Clear     :   IN  STD_LOGIC;
          Clock     :   IN  STD_LOGIC;
          HIGH      :   IN  STD_LOGIC;
          D         :   IN  STD_LOGIC;
          Q2        :   OUT STD_LOGIC;
          Q1        :   OUT STD_LOGIC;
          Q0        :   OUT STD_LOGIC;
          E         :   OUT STD_LOGIC);
   END COMPONENT;

   SIGNAL Q0        :   STD_LOGIC;
   SIGNAL HIGH      :   STD_LOGIC;
   SIGNAL D         :   STD_LOGIC;
   SIGNAL E         :   STD_LOGIC;
   SIGNAL Q1        :   STD_LOGIC;
   SIGNAL Q2        :   STD_LOGIC;
   SIGNAL Clear     :   STD_LOGIC;
   SIGNAL Clock     :   STD_LOGIC;

   constant clk_period : time := 10 ns;

BEGIN

   UUT: schematic PORT MAP(
        Q0 => Q0,
        HIGH => HIGH,
        D => D,
        E => E,
        Q1 => Q1,
        Q2 => Q2,
        Clear => Clear,
        Clock => Clock
   );
        D <= '0';
        HIGH <= '1';
        Clear <= '1';

    clk_process : process is
    begin
        Clock <= '0';
        wait for clk_period / 2;
        Clock <= '1';
        wait for clk_period / 2;
    end process clk_process;

   tb : PROCESS
   BEGIN
        Clear <= '0';

        for i in 0 to 7 loop
            for j in 0 to i loop
                D <= '0';
                wait for 5 ns;
            end loop;
            D <= '1';
            wait for 5 ns;
        end loop;

        Clear <= '1';
        wait for 1000 ns;
   END PROCESS;
END;