MS

// register
#define DEMCR (0xE000EDFC)
#define ITM_TER (0xE0000E00)
#define ITM_TCR (0xE0000E80)
#define ITM_PORT0 (0xE0000000)
#define ITM_PORT1 (0xE0000004)
#define ITM_LOCK_ACCESS (0xE0000FB0)

#define TPIU_ACPR (0xE0040010)
#define TPIU_SPPR (0xE00400F0)
#define TPIU_FFCR (0xE0040304)
#define TPIU_FFCR_FOnMan (1 << 6) // Manual flush

// flags
#define DEMCR_TRCENA 0x01000000
#define ITM_TCR_ITMENA 0x00000001
#define ITM_UNCLOCK_KEY 0xC5ACCE55

  // use 32 MHz external osc
  SysCtrlClockSet(true, false, SYS_CTRL_SYSDIV_32MHZ);





  // undocumented
  HWREG(0x44010010) = 0x1;
  // PB5 OUT
  HWREG(0x400DA400) |= 0x20;

  // DEMCR
  HWREG(DEMCR) |= DEMCR_TRCENA;

  // async output prescaler - 1
  HWREG(TPIU_ACPR) = 31;

  // Unlock
  HWREG(ITM_LOCK_ACCESS) = ITM_UNCLOCK_KEY;

  // Enable ITM
  HWREG(ITM_TCR) = ITM_TCR_ITMENA;
  // stimulus port 0 and 1 enable
  HWREG(ITM_TER) = 0x3;

  // NRZ format = 2, Manchester = 1 (reset value)
  HWREG(TPIU_SPPR) = 0x00000002;

  leds_init();


  while(0 == HWREG(ITM_PORT1));
  *(volatile uint32_t*)(ITM_PORT1) = 0xdeadc0de;

  char buff[] = "Hello, World!!!\n";

  /*
    * Each of the 32 stimulus ports has its own address.
    * A write to one of these locations causes data to be written
    *  into the FIFO if the corresponding bit in the Trace Enable
    *  Register is set.
    *  Reading from any of the stimulus ports returns the
    *  FIFO status in bit [0]:
    *  0 = full
    *  1 = not full
    */
  #if 1
  {
    char * iter = buff;
    while(*iter){
      while(0 == HWREG(ITM_PORT0));
      *(volatile char*)(ITM_PORT0) = *iter;
      iter++;
    };
  }
  #endif

  while(0 == HWREG(ITM_PORT1));
  *(volatile uint32_t*)(ITM_PORT1) = 0xdeadbeef;

  //
  // End here if return from main()
  //
  while(1)
  {
  }