1 --------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 --------------------------------------------
5 ENTITY string_detector IS
6 PORT ( d, clk, rst: IN BIT;
7 q: OUT BIT);
8 END string_detector;
9 --------------------------------------------
10 ARCHITECTURE my_arch OF string_detector IS
11 TYPE state IS (zero, one, two, three);
12 SIGNAL pr_state, nx_state: state;
13 BEGIN
14 ----- Lower section: --------------------
15 PROCESS (rst, clk)
16 BEGIN
17 IF (rst='1') THEN
18 pr_state <= zero;
19 ELSIF (clk'EVENT AND clk='1') THEN
20 pr_state <= nx_state;
21 END IF;
22 END PROCESS;
23 ---------- Upper section: ---------------
24 PROCESS (d, pr_state)
25 BEGIN
26 CASE pr_state IS
27 WHEN zero =>
28 q <= '0';
29 IF (d='1') THEN nx_state <= one;
30 ELSE nx_state <= zero;
31 END IF;
32 WHEN one =>
33 q <= '0';
34 IF (d='1') THEN nx_state <= two;
35 ELSE nx_state <= zero;
36 END IF;
37 WHEN two =>
38 q <= '0';
39 IF (d='1') THEN nx_state <= three;
40 ELSE nx_state <= zero;
41 END IF;
42 WHEN three =>
43 q <= '1';
44 IF (d='0') THEN nx_state <= zero;
45 ELSE nx_state <= three;
46 END IF;
47 END CASE;
48 END PROCESS;
49 END my_arch;
50 --------------------------------------------