Dual Port Ram with combined R/W signals

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity dual_port_ram_rwc is
generic(
    address_length: natural := 8;
    data_length: natural := 8
);
port(
    clock: in std_logic;
    mem_enable: in std_logic;
    -- first port
    port1_enable: in std_logic;
    rw1_enable: in std_logic;
    address1: in std_logic_vector((address_length - 1) downto 0);
    data_input1: in std_logic_vector ((data_length - 1) downto 0);
    data_output1: out std_logic_vector ((data_length - 1) downto 0);
    -- second port
    port2_enable: in std_logic;
    rw2_enable: in std_logic;
    address2: in std_logic_vector((address_length - 1) downto 0);
    data_input2: in std_logic_vector ((data_length - 1) downto 0);
    data_output2: out std_logic_vector ((data_length - 1) downto 0)
);
end dual_port_ram_rwc;

architecture arch of dual_port_ram_rwc is
    type ram_type is array (0 to (2**(address_length) -1)) of std_logic_vector((data_length - 1) downto 0);
    signal ram: ram_type;
    signal temp_address1: std_logic_vector((address_length - 1) downto 0);
    signal temp_address2: std_logic_vector((address_length - 1) downto 0);
begin

process(clock) is
begin
    if rising_edge(clock)and mem_enable = '1' then
        -- port 1
        if(port1_enable = '1') then
            if(rw1_enable = '0') then
                temp_address1 <= address1;
            elsif (rw1_enable = '1') then
                ram(conv_integer(unsigned(address1))) <= data_input1;
            end if;
            data_output1 <= ram(conv_integer(unsigned(temp_address1)));
        end if;
        -- port 2
        if(port2_enable = '1') then
            if(rw2_enable = '0') then
                temp_address2 <= address2;
            elsif (rw2_enable = '1') then
                ram(conv_integer(unsigned(address2))) <= data_input2;
            end if;
            data_output2 <= ram(conv_integer(unsigned(temp_address2)));
        end if;
    end if;

end process;

end arch;