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Dual Port Ram with combined R/W signals

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May 30th, 2018
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VHDL 1.78 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4.  
  5. entity dual_port_ram_rwc is
  6. generic(
  7.     address_length: natural := 8;
  8.     data_length: natural := 8
  9. );
  10. port(
  11.     clock: in std_logic;
  12.     mem_enable: in std_logic;
  13.     -- first port
  14.     port1_enable: in std_logic;
  15.     rw1_enable: in std_logic;
  16.     address1: in std_logic_vector((address_length - 1) downto 0);
  17.     data_input1: in std_logic_vector ((data_length - 1) downto 0);
  18.     data_output1: out std_logic_vector ((data_length - 1) downto 0);
  19.     -- second port
  20.     port2_enable: in std_logic;
  21.     rw2_enable: in std_logic;
  22.     address2: in std_logic_vector((address_length - 1) downto 0);
  23.     data_input2: in std_logic_vector ((data_length - 1) downto 0);
  24.     data_output2: out std_logic_vector ((data_length - 1) downto 0)
  25. );
  26. end dual_port_ram_rwc;
  27.  
  28. architecture arch of dual_port_ram_rwc is
  29.     type ram_type is array (0 to (2**(address_length) -1)) of std_logic_vector((data_length - 1) downto 0);
  30.     signal ram: ram_type;
  31.     signal temp_address1: std_logic_vector((address_length - 1) downto 0);
  32.     signal temp_address2: std_logic_vector((address_length - 1) downto 0);
  33. begin
  34.  
  35. process(clock) is
  36. begin
  37.     if rising_edge(clock)and mem_enable = '1' then
  38.         -- port 1
  39.         if(port1_enable = '1') then
  40.             if(rw1_enable = '0') then
  41.                 temp_address1 <= address1;
  42.             elsif (rw1_enable = '1') then
  43.                 ram(conv_integer(unsigned(address1))) <= data_input1;
  44.             end if;
  45.             data_output1 <= ram(conv_integer(unsigned(temp_address1)));
  46.         end if;
  47.         -- port 2
  48.         if(port2_enable = '1') then
  49.             if(rw2_enable = '0') then
  50.                 temp_address2 <= address2;
  51.             elsif (rw2_enable = '1') then
  52.                 ram(conv_integer(unsigned(address2))) <= data_input2;
  53.             end if;
  54.             data_output2 <= ram(conv_integer(unsigned(temp_address2)));
  55.         end if;
  56.     end if;
  57.    
  58. end process;
  59.  
  60. end arch;
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