LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_signed.all;

ENTITY Lab5 is
    Port ( A    :   in   STD_LOGIC_VECTOR(3 downto 0);      --A input
           B    :   in   STD_LOGIC_VECTOR(3 downto 0);      --B input
           Op   :   in   STD_LOGIC_VECTOR(1 downto 0);
           R    :   out  STD_LOGIC_VECTOR(7 downto 0));
    END ENTITY;


ARCHITECTURE test OF Lab5 IS

SIGNAL A_times_B        : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL A_minus_B        : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL A_plus_B         : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL A_divides_B  : SIGNED(7 downto 0);
SIGNAL SA, SB, SigR  : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

SA <=  A(3) & A(3) & A(3) & A(3) & A;
SB <=  B(3) & B(3) & B(3) & B(3) & B;
R <= SigR;

    A_plus_B    <= SA + SB;
    A_minus_B   <= SA + (NOT (SB) + '1');
    A_times_B   <= A * B;
    A_divides_B <= (SIGNED(SA)) / (SIGNED(SB));



operation_select: PROCESS(Op, A_plus_B, A_minus_B, A_times_B, A_divides_B)
    BEGIN

        CASE Op IS
            WHEN "00"   => SigR <= A_plus_B;
            WHEN "01"   => SigR <= A_minus_B;
            WHEN "10"   => SigR <= A_times_B;
            WHEN OTHERS => SigR <= STD_LOGIC_VECTOR(A_divides_B);
        END CASE;
    END PROCESS;

END ARCHITECTURE;