VHDL BMSTU HW

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test IS
END test;

ARCHITECTURE behavior OF test IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control_unit
PORT(
   U : IN std_logic_vector(5 downto 0);
   clk : IN std_logic;
   rst : IN std_logic;
   V : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal U : std_logic_vector(5 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal V : std_logic_vector(7 downto 1);
-- Clock period definitions
constant clk_period : time := 10ns;

BEGIN
   -- Instantiate the Unit Under Test (UUT)
   uut: control_unit PORT MAP (
      U => U,
      clk => clk,
      rst => rst,
      V => V
   );

   -- Clock process definitions
   clk_process : process
   begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100ns.
      rst<='1';
      wait for 100ns;
      rst<='0';
      wait for clk_period*10;
      -- insert stimulus here
      U<="000000";
      wait for clk_period;
      U<="110100";
      wait for clk_period;
      U<="111111";
      wait for clk_period;
      U<="111111";
      wait for clk_period;
      wait;
   end process;
END;