q1_lista04

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
port(w0,w1,w2,w3:   in std_logic;
       s0,s1:       in std_logic;
           k:       out std_logic);
end mux4_1;

architecture comp of mux4_1 is

begin
  process(w0,w1,w2,w3,s0,s1)
    begin
    if s0 ='0' and s1 ='0' then k <= w0;
        elsif s0 ='1' and s1 ='0' then k <= w1;
        elsif s0 ='0' and s1='1' then k <= w2;
        else k <=w3;
    end if;
  end process;
end comp;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_16_4 is
  port(
      entrada:  in std_logic_vector(15 downto 0);
      selecao:  in std_logic_vector(3 downto 0);
      z:    out std_logic
      );
end  mux_16_4;

architecture comp_mux_16_1 of mux_16_4 is

    signal z1, z2, z3, z4   :std_logic;

    component mux4_1 is
        port(w0,w1,w2,w3:   in std_logic;
                s0,s1:      in std_logic;
                    k:      out std_logic);
    end component;

    begin
        m1: mux4_1 port map(entrada(0),entrada(1),entrada(2),entrada(3),selecao(0),selecao(1),z1);
        m2: mux4_1 port map(entrada(4),entrada(5),entrada(6),entrada(7),selecao(0),selecao(1),z2);
        m3: mux4_1 port map(entrada(8),entrada(9),entrada(10),entrada(11),selecao(0),selecao(1),z3);
        m4: mux4_1 port map(entrada(12),entrada(13),entrada(14),entrada(15),selecao(0),selecao(1),z4);
        m5: mux4_1 port map(z1,z2,z3,z4,selecao(2),selecao(3),z);
end comp_mux_16_1;