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-- Company:
-- Engineer:
--
-- Create Date: 09.04.2018 08:30:38
-- Design Name:
-- Module Name: PWM_driver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PWM_driver is
    Generic ( CNT_WIDTH   : INTEGER := 256
             -- NUM_OUTPUTS : INTEGER
              );
    Port    ( clk    : in STD_LOGIC;
              ce     : in STD_LOGIC;
              --duty_i : in UNSIGNED (6 DOWNTO 0); --STD_LOGIC_VECTOR (6 DOWNTO 0);
              pwm_o  : out STD_LOGIC--_VECTOR ((NUM_OUTPUTS-1) TO 0)
              );
end PWM_driver;

architecture Behavioral of PWM_driver is

    constant duty : UNSIGNED(6 DOWNTO 0) := TO_UNSIGNED(50,7);

    signal counter  : UNSIGNED (31 downto 0):= X"00000000";
    signal pwm      : STD_LOGIC;
    signal pwm_v    : STD_LOGIC_VECTOR (0 DOWNTO 0);
    signal duty_i : UNSIGNED (6 DOWNTO 0);
    COMPONENT ila_0
    PORT (
        clk : IN STD_LOGIC;
        probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
    );
    END COMPONENT  ;

begin

    duty_i <= duty;

    process(clk) begin
        if rising_edge(clk) then
            if ce = '1' then
                if counter < CNT_WIDTH then
                    counter <= counter + 1;
                    if counter < (CNT_WIDTH*TO_INTEGER(duty_i)/100) then
                        pwm <= '1';
                    else
                        pwm <= '0';
                    end if;
                else
                    counter <= X"00000000";
                    pwm <= '1';
                end if;
            end if;
        end if;
    end process;


    pwm_v(0) <= pwm;
    your_instance_name : ila_0
    PORT MAP (
        clk => clk,
        probe0 => pwm_v
    );


end Behavioral;