architecture Behavioral of PC is

    type state is (idle, init, subtract, test, operation_sub1, operation_sub0, correction, finished);
    signal current_state, next_state : state;

begin

    control:    process(current_state, start, S_in, counted)
                begin
                    en_M <= '0';
                    en_Q <= '0';
                    en_A <= '0';
                    en_C <= '0';
                    en_S <= '0';
                    reset_M <= '1';
                    reset_Q <= '1';
                    reset_A <= '1';
                    reset_C <= '1';
                    reset_S <= '1';
                    shift <= '0';
                    stop <= '0';
                    start_out <= '0';
                    sub <= '0';

                    case current_state is
                        when idle =>
                            if start='1' then
                                reset_M <= '0';
                                reset_Q <= '0';
                                reset_A <= '0';
                                reset_C <= '0';
                                reset_S <= '0';
                                next_state <= init;
                            else
                                next_state <= idle;
                            end if;

                        when init =>
                            en_A <= '1'; -- "A" carica i MSB del dividendo
                            en_Q <= '1'; -- "Q" carica i LSB del dividendo
                            en_M <= '1'; -- "M" carica il divisore
                            reset_S <= '0';
                            start_out <= '1';
                            next_state <= subtract;

                        when subtract =>
                            en_A <= '1';
                            en_M <= '1';
                            en_S <= '1';
                            sub <= '1';
                            next_state <= test;

                        when test => -- shift
                            en_Q <= '1';
                            shift <= '1';
                            en_C <= '1';

                            if counted=N/2-1 then
                                if S_in='0' then
                                    sub <= '1';
                                    next_state <= finished;
                                else
                                    sub <= '0'; --
                                    next_state <= correction;
                                end if;
                            else
                                en_A <= '1';
                                en_S <= '1';

                                if S_in='0' then
                                    sub <= '1';
                                    next_state <= operation_sub1;
                                else
                                    sub <= '0'; --
                                    next_state <= operation_sub0;
                                end if;
                            end if;

                        when operation_sub1 =>
                            en_A <= '1';
                            en_M <= '1';
                            en_S <= '1';
                            sub <= '1';
                            next_state <= test;

                        when operation_sub0 =>
                            en_A <= '1';
                            en_M <= '1';
                            en_S <= '1';
                            sub <= '0'; --
                            next_state <= test;

                        when correction =>
                            if S_in='1' then
                                en_A <= '1';
                                en_M <= '1';
                                sub <= '0'; --
                            else
                                sub <= '1';
                            end if;

                            next_state <= finished;

                        when finished =>
                            stop <= '1';
                            next_state <= idle;
                    end case;
                end process;

    update:     process(clk_in, next_state)
                begin
                    if rising_edge(clk_in) then
                        current_state <= next_state;
                    end if;
                end process;

end Behavioral;