Mik32+UART1+IRQ

#include "scr1_csr_encoding.h"
#include "riscv_csr_encoding.h"
#include "mik32_memory_map.h"
#include "power_manager.h"
#include "pad_config.h"
#include "epic.h"
#include "uart.h"

volatile uint32_t ddd;

void trap_handler(void)
{

    if (EPIC->RAW_STATUS & (1<<EPIC_UART_1_INDEX))  {

       if(UART_1->FLAGS & UART_FLAGS_RXNE_M)
         {
            ddd = UART_1->RXDATA;
            UART_1->TXDATA = ddd;
         }
    }
}


int main()
{

    PM->CLK_APB_M_SET |= PM_CLOCK_APB_M_EPIC_M;
    PM->CLK_APB_P_SET |= PM_CLOCK_APB_P_UART_1_M | PM_CLOCK_APB_P_GPIO_1_M ;

    PAD_CONFIG->PORT_1_CFG  = (PAD_CONFIG->PORT_1_CFG  & ~(PAD_CONFIG_PIN_M(8) | PAD_CONFIG_PIN_M(9))) \
                               | PAD_CONFIG_PIN(8,0x01) | PAD_CONFIG_PIN(9,0x01);

    UART_1->CONTROL1 = 0;
    UART_1->DIVIDER  = 32000000/115200;

    UART_1->CONTROL2 = 0;
    UART_1->CONTROL3 = 0;
    UART_1->CONTROL1 = UART_CONTROL1_TE_M | UART_CONTROL1_RE_M | UART_CONTROL1_M_8BIT_M | UART_CONTROL1_UE_M;

    EPIC->MASK_LEVEL_SET = 1 << EPIC_UART_1_INDEX;

    UART_1->CONTROL1 |= UART_CONTROL1_RXNEIE_M;

    // global interrupt enable
    set_csr(mstatus, MSTATUS_MIE);  // Global interrupt enable
    set_csr(mie, MIE_MEIE);         // Machine External Interrupt Enable

    while (1)
    {

    }
}