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GBA APU

xiahanlu
Jan 28th, 2019
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  1.  
  2. /* Channel 1, 2 dual-wave channels (Channel 1 supports "real-time" frequency conversion scanning) */
  3. /* In GBC/GB games, it is usually used as the main melody channel. */
  4. struct channel_squ {
  5.   int32_t sweep_phase; /* Frequency scan basic timestamp (based on CPU clock cycle) */
  6.   int32_t sweep_trigger; /* Frequency scan update clock point (based on CPU clock cycle) */
  7.   int32_t signal_phase; /* Square wave signal updates the basic timestamp (based on CPU clock cycle).
  8.                                          One f (x) of the waveform, that is, one hz,
  9.                                          scans eight points of the current square wave duty cycle (based on CPU clock cycle). */
  10.   int32_t signal_trigger; /* Square wave signal update clock point (based on CPU clock cycle) */
  11.   int32_t length_phase; /* Basic time stamp of square wave signal sound length (based on CPU clock cycle) */
  12.   int32_t length_trigger; /* Square wave signal length update clock point (based on CPU clock cycle) */
  13.   int32_t envlope_phase; /* Square wave signal envelope basic timestamp (based on CPU clock cycle) */
  14.   int32_t envlope_trigger; /* Square wave envelope update clock point (based on CPU clock cycle) */
  15.   int32_t signal_output; /* Square wave signal output, note. As a level signal, only 0 or 1 will be output. */
  16.   int32_t signal_volume; /* Signal amplification, also known as Volume. */
  17.   int32_t duty_poll; /* Duty ratio look-up count, which essentially changes tone color, but also has a role in internal frequency division */
  18.   int32_t length_count;/* Length counter */
  19.   uint8_t *duty_vec; /* Square wave duty ratio vector table */
  20.   uint16_t nrx0; /* Square-wave correlation registers used by GBA (sweep frequency) */
  21.   uint16_t nrx1_x2; /* Square-wave correlation registers used by GBA (duty cycle/length/envelope [GBC NR register merge]) */
  22.   uint16_t nrx3_x4; /* Square wave correlation registers used by GBA (restart/channel frequency write [high bit] [GBC NR register merge]) */
  23.   uint8_t duty[4][8]; /* Duty ratio table, placed internally to facilitate Cache correlation */
  24. };
  25. /* Channel 3: 4-bit waveform
  26. /* In GBC/GB games, it is usually used as configurable waveforms,
  27.    such as triangular/sinusoidal synthesis, and can also play some bad voices? */
  28. struct channel_wave {
  29.   int32_t output_phase; /* Waveform update basic timestamp (based on CPU clock cycle) */
  30.   int32_t output_trigger; /* Waveform update clock point, once f (x), that is, 1 Hz will scan 32/64 waveform scan points (based on CPU clock cycle) */
  31.   int32_t length_phase; /* Waveform tone length basic timestamp (based on CPU clock cycle) */
  32.   int32_t length_trigger; /* Waveform length update clock point (based on CPU clock cycle) */
  33.   int32_t length_count;/* Length counter */
  34.   int32_t counter; /* Waveform playback count */
  35.   uint8_t qram[64];  /* 4-bit waveform correlation register used by GBA (PCM4-bit waveform writing) */
  36.   uint16_t xram[16];  /* 4-bit waveform correlation register used by GBA (PCM4-bit waveform writing) */
  37.   uint16_t nr30; /* 4-bit waveform-related registers used by GBA (channel switch/bank mode selection) */
  38.   uint16_t nr31_32; /* 4-bit waveform-related registers used by GBA (length/volume) */
  39.   uint16_t nr33_34; /* 4-bit waveform-related registers used by GBA (frequency/control) */
  40. };
  41. /* Channel 4: LFSR Random noise */
  42. /* Used as special effects and some simple drums in GBC/GB games. */
  43. struct channel_noise {
  44.   int32_t signal_phase; /* Noise signal update basic timestamp (based on CPU clock cycle) */
  45.   int32_t signal_trigger; /* Noise signal update clock point (based on CPU clock cycle) */
  46.   int32_t length_phase; /* Noise length update basic timestamp (based on CPU clock cycle) */
  47.   int32_t length_trigger; /* Noise length update clock point (based on CPU clock cycle) */
  48.   int32_t envlope_phase; /* Noise envelope update basic timestamp (based on CPU clock cycle) */
  49.   int32_t length_count;/* Length counter */
  50.   int32_t envlope_trigger; /* Noise envelope update clock point (based on CPU clock cycle) */
  51.   int32_t signal_output; /* Noise signal output, note. As a level signal, only 0 or 1 will be output. */
  52.   int32_t signal_volume; /* Signal amplification, also known as Volume. */
  53.   uint16_t nr41_42; /* Noise-related registers used by GBA (length/envelope) */
  54.   uint16_t nr43_44; /* Noise-related registers used by GBA (frequency/control) */
  55. };
  56. /* Channel 5, 6 FIFO, 8-bit signed PCM, with the same name as DirectSound in Microsoft DirectX. */
  57. /* The strongest vocal channel, supporting 8Bit PCM,
  58.    you can even use to play some clear voices, (Namco's Tales of Phantasia OP in GBA)  */
  59. struct channel_fifo {
  60.   int8_t buf [32]; /* PCM ring buffer */
  61.   int8_t write; /* PCM write location */
  62.   int8_t count; /* PCM effective count */
  63.   int8_t read; /* PCM read location */
  64. };
  65. /* Channel master control/settings */
  66. struct channel_control {
  67.   uint16_t nr50_51;
  68.   uint16_t nr52;
  69.   uint16_t snd_ctl;
  70.   uint16_t pwm_ctl;
  71. };
  72. /* Synthesizer for GBA (based on GBC, adding two 8-bit PCM channels) */
  73. struct apu {
  74.   struct channel_squ squ_ch[2];
  75.   struct channel_wave wave_ch;
  76.   struct channel_noise noise_ch;
  77.   struct channel_fifo fifo_ch[2];
  78.   struct channel_control settings;
  79.   uint8_t pcm_buf[8 * APU_INTERNAL_BUFFER_N * APU_SAMPLE_FREQ_MAX / 59]; /* 8:max size (float) * channel 2 */
  80.   uint32_t sam_bstop;
  81.   uint32_t sam_bstart;
  82.   uint32_t sam_pointer;
  83.   struct gba *agb;
  84. };
  85. struct gba {
  86.   struct arm7 arm7;
  87.   struct controller joypad;
  88.   struct timer timer;
  89.   struct apu apu;
  90.   struct dma dma;
  91.   struct gpu gpu;
  92.   struct cart cart;
  93.   struct serial sio;
  94.   struct dev_infos *dfs;
  95.  
  96.   uint32_t mctl;
  97.   uint16_t mwait;
  98.   uint8_t postf;
  99.   uint32_t cache_ptr; /* I'm not really sure about the detailed caching information of the GBA machine. */
  100.  
  101.   uint8_t SRam[0x10000+32];
  102.   uint8_t PRom[0x400*0x400*32+32];
  103.   uint8_t WRam[0x400*256+32];
  104.   uint8_t IRam[0x400*32+32];
  105.   uint8_t bios[0x400*16+32];
  106.   uint8_t IOMap[0x800+32];
  107.  
  108.   uint8_t wram_wait;
  109.   uint8_t sram_wait;
  110.   uint8_t noseq_wait0;
  111.   uint8_t seq_wait0;
  112.   uint8_t noseq_wait1;
  113.   uint8_t seq_wait1;
  114.   uint8_t noseq_wait2;
  115.   uint8_t seq_wait2;
  116.  
  117.   uint8_t sram_wait_t[4];
  118.   uint8_t noseq_wait0_t[4];
  119.   uint8_t seq_wait0_t[2];
  120.   uint8_t noseq_wait1_t[4];
  121.   uint8_t seq_wait1_t[2];
  122.   uint8_t noseq_wait2_t[4];
  123.   uint8_t seq_wait2_t[2];
  124.  
  125.   int32_t clks_oft;
  126.   int32_t clks_cpu_ct;
  127. };
  128.  
  129. uint8_t callstd agb_mbus_rb_seq (struct gba *agb, uint32_t addr);
  130. uint8_t callstd agb_mbus_rb_noseq (struct gba *agb, uint32_t addr);
  131. uint16_t callstd agb_mbus_rhw_seq (struct gba *agb, uint32_t addr);
  132. uint16_t callstd agb_mbus_rhw_noseq (struct gba *agb, uint32_t addr);
  133. uint32_t callstd agb_mbus_rw_noseq (struct gba *agb, uint32_t addr);
  134. uint32_t callstd agb_mbus_rw_seq (struct gba *agb, uint32_t addr);
  135. void callstd agb_mbus_wb_noseq (struct gba *agb, uint32_t addr, uint8_t value);
  136. void callstd agb_mbus_wb_seq (struct gba *agb, uint32_t addr, uint8_t value);
  137. void callstd agb_mbus_whw_noseq (struct gba *agb, uint32_t addr, uint16_t value);
  138. void callstd agb_mbus_whw_seq (struct gba *agb, uint32_t addr, uint16_t value);
  139. void callstd agb_mbus_ww_noseq (struct gba *agb, uint32_t addr, uint32_t value);
  140. void callstd agb_mbus_ww_seq (struct gba *agb, uint32_t addr, uint32_t value);
  141. uint16_t callstd agb_code_rhw_seq (struct gba *agb, uint32_t addr) ;
  142. uint16_t callstd agb_code_rhw_noseq (struct gba *agb, uint32_t addr) ;
  143. uint32_t callstd agb_code_rw_seq (struct gba *agb, uint32_t addr);
  144. uint32_t callstd agb_code_rw_noseq (struct gba *agb, uint32_t addr);
  145. void callstd agb_gamepak_prefetch (struct gba *agb, uint32_t addr, uint32_t internal_clks);
  146.  
  147. finline
  148. void check_halt (struct gba *agb, int int_mask) {
  149.   if ((agb->arm7.halt & 0x80000001) == 0x80000001)
  150.     if (agb->arm7.ime & int_mask)
  151.       agb->arm7.halt &= ~1;
  152.     else ;
  153.   else ;
  154. }
  155.  
  156. finline
  157. void check_stop (struct gba *agb, int int_mask) {
  158.   if ((agb->arm7.halt & 0x80000001) == 0x00000001)
  159.     if (agb->arm7.ime & int_mask)
  160.       agb->arm7.halt &= ~1;
  161.     else ;
  162.   else ;
  163. }
  164.  
  165. #include "gba.inl"
  166. #include "dma.inl"
  167.  
  168. finline
  169. void squ_render (struct apu *apu, int ch, int32_t delta) {
  170.   if ((apu->settings.nr52 & 0x80)) {
  171.     if (!(apu->settings.nr52 & (1 << (ch & 1))))
  172.       return ;
  173.     else {
  174.       struct channel_squ *squ = & apu->squ_ch[ch & 1];
  175.       /* squ signal */
  176.       squ->signal_phase += delta;
  177.       if (squ->signal_phase >= squ->signal_trigger) {
  178.         squ->duty_poll += squ->signal_phase / squ->signal_trigger;
  179.         squ->signal_phase %= squ->signal_trigger;
  180.       }
  181.       /* squ envlope */
  182.       if ((squ->nrx1_x2 >> 8) & 7) {
  183.         squ->envlope_phase += delta;
  184.         if (squ->envlope_phase >= squ->envlope_trigger) {
  185.           squ->envlope_phase %= squ->envlope_trigger;
  186.           if (squ->nrx1_x2 & 0x800) {
  187.             squ->signal_volume += squ->envlope_phase / squ->envlope_trigger;
  188.             if (squ->signal_volume > 15)
  189.               squ->signal_volume = 15;
  190.           } else {
  191.             squ->signal_volume -= squ->envlope_phase / squ->envlope_trigger;
  192.             if (squ->signal_volume < 0) {
  193.   #ifdef NR_SQU_TEST1
  194.               apu->settings.nr52 &= ~(1 << (ch & 1));
  195.   #endif
  196.               squ->signal_volume = 0;
  197.             }
  198.           }
  199.         }
  200.       }
  201.       /* length count */
  202.       squ->length_phase += delta;
  203.       if (squ->length_phase > squ->length_trigger) {
  204.         squ->length_count -= squ->length_phase/ squ->length_trigger;
  205.         squ->length_phase %= squ->length_trigger;
  206.         if (squ->length_count <= 0) {
  207.           squ->length_count = 0;
  208.           if (squ->nrx3_x4 & 0x4000)
  209.             apu->settings.nr52 &= ~(1 << (ch & 1));
  210.         }
  211.       }
  212.       /* freq sweep */
  213.       if (!ch && (squ->nrx0 >> 4) & 7) {
  214.         squ->sweep_phase += delta;
  215.         if (squ->sweep_phase >= squ->sweep_trigger) {
  216.            int _freq_n = squ->nrx3_x4 & 0x3FF;
  217.            int _freq_s = _freq_n;
  218.            int _block_n = squ->sweep_phase/ squ->sweep_trigger;
  219.            squ->sweep_phase %= squ->sweep_trigger;
  220.            if (squ->nrx0 & 8)  
  221.              while (_block_n-- > 0)
  222.                _freq_n = (int) ((double) _freq_n - (double) _freq_n  / (double)(1 << (squ->nrx0 & 7)));
  223.            else
  224.               while (_block_n-- > 0)
  225.                _freq_n = (int) ((double) _freq_n + (double) _freq_n  / (double)(1 << (squ->nrx0 & 7)));
  226.            if (_freq_n <= 0)
  227.              _freq_n = _freq_s;
  228.            else if (_freq_n > 2047) {
  229.              _freq_n = 2047; /* FIXME: right ??, i don't know */
  230.              apu->settings.nr52 &= ~(1 << (ch & 1));
  231.            }
  232.            /* signal_trigger calc := cpu freq/ chan freq / duty 8 divider
  233.                chan freq (hz):= 131072/(2048 - ch's freq data )
  234.            */
  235.            squ->signal_trigger = (int)((16780000.0/ 131072.0 / (double)(2048 - _freq_n)) / 8.0);
  236.            if (squ->signal_phase >= squ->signal_trigger) {
  237.               squ->duty_poll += squ->signal_phase / squ->signal_trigger;
  238.               squ->signal_phase %= squ->signal_trigger;
  239.            }
  240.         }
  241.       }
  242.     }
  243.   }
  244. }
  245.  
  246. finline
  247. void wave_render (struct apu *apu, int32_t delta) {
  248.   if ((apu->settings.nr52 & 0x84) == 0x84
  249.     && (apu->wave_ch.nr30 & 0x80) == 0x80) {
  250.       struct channel_wave *wav = & apu->wave_ch;
  251.       /* wave out */
  252.       wav->output_phase += delta;
  253.       if (wav->output_phase >= wav->output_trigger) {
  254.         wav->counter += wav->output_phase / wav->output_trigger;
  255.         wav->output_phase %= wav->output_trigger;
  256.       }
  257.       /* length count */
  258.       wav->length_phase += delta;
  259.       if (wav->length_phase > wav->length_trigger) {
  260.         wav->length_count -= wav->length_phase/ wav->length_trigger;
  261.         wav->length_phase %= wav->length_trigger;
  262.         if (wav->length_count <= 0) {
  263.           wav->length_count = 0;
  264.           if (wav->nr33_34 & 0x4000)
  265.             apu->settings.nr52 &= ~4;
  266.         }
  267.       }
  268.   }
  269. }
  270.  
  271. finline
  272. intptr_t lfsr15 (intptr_t seed) {
  273.   /* step15 lfsr: 15, 14 (14,13)*/
  274.   intptr_t d2 = (seed & 0x4000) >> 14;
  275.   intptr_t d3 = (seed & 0x2000) >> 13;
  276.   intptr_t out = 1 & (d2 ^ d3);
  277.   seed <<= 1;
  278.   seed |= out;
  279.   seed &= 0x7FFF;
  280.   return seed;
  281. }
  282. finline
  283. intptr_t lfsr7 (intptr_t seed) {
  284.   /* step7 lfsr: 7, 6 (6,5)*/
  285.   intptr_t d2 = (seed & 0x40) >> 6;
  286.   intptr_t d3 = (seed & 0x20) >> 5;
  287.   intptr_t out = 1 & (d2 ^ d3);
  288.   seed <<= 1;
  289.   seed |= out;
  290.   seed &= 0x7F;
  291.   return seed;
  292. }
  293. finline
  294. void noi_render (struct apu *apu, int32_t delta) {
  295.   if ((apu->settings.nr52 & 0x88) == 0x88) {
  296.     struct channel_noise *noi = & apu->noise_ch;
  297.     /* noi signal */
  298.     noi->signal_phase += delta;
  299.     if (noi->signal_phase >= noi->signal_trigger) {
  300.       int n_block = noi->signal_phase / noi->signal_trigger;
  301.       noi->signal_phase %= noi->signal_trigger;
  302.       while (n_block-- > 0)
  303.         noi->signal_output = (noi->nr43_44 & 8)
  304.             ? lfsr7 (noi->signal_output & 0x7F)
  305.                  : lfsr15 (noi->signal_output & 0x7FFF);
  306.     }
  307.     /* noise envlope */
  308.     if ((noi->nr41_42 >> 8) & 7) {
  309.       noi->envlope_phase += delta;
  310.       if (noi->envlope_phase >= noi->envlope_trigger) {
  311.         noi->envlope_phase %= noi->envlope_trigger;
  312.         if (noi->nr41_42 & 0x800) {
  313.           noi->signal_volume += noi->envlope_phase / noi->envlope_trigger;
  314.           if (noi->signal_volume > 15)
  315.             noi->signal_volume = 15;
  316.         } else {
  317.           noi->signal_volume -= noi->envlope_phase / noi->envlope_trigger;
  318.           if (noi->signal_volume < 0) {
  319. #ifdef NR_NOI_TEST1
  320.             apu->settings.nr52 &= ~(1 << (ch & 1));
  321. #endif
  322.             noi->signal_volume = 0;
  323.           }
  324.         }
  325.       }
  326.     }
  327.     /* length count */
  328.     noi->length_phase += delta;
  329.     if (noi->length_phase > noi->length_trigger) {
  330.       noi->length_count -= noi->length_phase/ noi->length_trigger;
  331.       noi->length_phase %= noi->length_trigger;
  332.       if (noi->length_count <= 0) {
  333.         noi->length_count = 0;
  334.         if (noi->nr43_44 & 0x4000)
  335.           apu->settings.nr52 &= ~8;
  336.       }
  337.     }
  338.   }
  339. }
  340.  
  341. finline
  342. void apu_clks (struct apu *apu, int32_t delta) {
  343. }
  344. finline
  345. uint16_t apu_read (struct apu *apu, uint32_t addr) {
  346.   /* TODO: NR MASK */
  347.   switch (addr & 0x3FF) {
  348.   case 0x060: return apu->squ_ch[0].nrx0;
  349.   case 0x062: return apu->squ_ch[0].nrx1_x2;
  350.   case 0x064: return apu->squ_ch[0].nrx3_x4;
  351.   case 0x068: return apu->squ_ch[1].nrx1_x2;
  352.   case 0x06C: return apu->squ_ch[1].nrx3_x4;
  353.   case 0x070: return apu->wave_ch.nr30;
  354.   case 0x072: return apu->wave_ch.nr31_32;
  355.   case 0x074: return apu->wave_ch.nr33_34;
  356.   case 0x078: return apu->noise_ch.nr41_42;
  357.   case 0x07C: return apu->noise_ch.nr43_44;
  358.   case 0x080: return apu->settings.nr50_51;
  359.   case 0x082: return apu->settings.snd_ctl;
  360.   case 0x084: return apu->settings.nr52;
  361.   case 0x088: return apu->settings.pwm_ctl;
  362.   case 0x090: case 0x0092: case 0x094: case 0x096:
  363.   case 0x098: case 0x009A: case 0x09C:
  364.   case 0x09E: return apu->wave_ch.xram[((addr - 0x090 & 0x3FF) >> 1) + (apu->wave_ch.nr30 & 0x40) ? 0 : 8];
  365.   default:
  366.     DEBUG_BREAK ();
  367.   }
  368.   return 0;
  369. }
  370. finline
  371. void apu_write (struct apu *apu, uint32_t addr, uint16_t value) {
  372.  
  373.   switch (addr & 0x3FF) {
  374.   case 0x060:
  375.     apu->squ_ch[0].nrx0 = value;
  376.     break;
  377.   case 0x062:
  378.     apu->settings.nr52 |= 1;
  379.     apu->squ_ch[0].nrx1_x2 = value;
  380.     apu->squ_ch[0].duty_vec = & apu->squ_ch[0].duty[value >> 6 & 3][0];
  381.     apu->squ_ch[0].signal_volume = value >> 12;
  382.     apu->squ_ch[0].length_count = 64 - (value & 63);
  383.     apu->squ_ch[0].length_trigger = 16780000/256;
  384.     apu->squ_ch[0].envlope_trigger = 16780000/64 * (apu->squ_ch[0].nrx1_x2 >> 8 & 7);;
  385.     break;
  386.   case 0x068:
  387.     apu->settings.nr52 |= 2;
  388.     apu->squ_ch[1].nrx1_x2 = value;
  389.     apu->squ_ch[1].duty_vec = & apu->squ_ch[1].duty[value >> 6 & 3][0];
  390.     apu->squ_ch[1].signal_volume = value >> 12;
  391.     apu->squ_ch[1].length_count = 64 - (value & 63);
  392.     apu->squ_ch[1].length_trigger = 16780000/256;
  393.     apu->squ_ch[1].envlope_trigger = 16780000/64* (apu->squ_ch[1].nrx1_x2 >> 8 & 7);;
  394.     break;
  395.   case 0x064:
  396.     if (value & 0x8000) {
  397.       apu->settings.nr52 |= 1;
  398.         /*  Trigger Event
  399.          *  Writing a value to NRx4 with bit 7 set causes the following things to occur:
  400.          *
  401.          *  Channel is enabled (see length counter).
  402.          *  If length counter is zero, it is set to 64
  403.          *  Frequency timer is reloaded with period.
  404.          *  Volume envelope timer is reloaded with period.
  405.          *  Channel volume is reloaded from NRx2.
  406.          *  Square 1's sweep does several things
  407.          *  Note that if the channel's DAC is off, after the above actions occur the channel will be immediately disabled again.
  408.  
  409.         /*  During a trigger event, several things occur:
  410.  
  411.             Square 1's frequency is copied to the shadow register.
  412.             The sweep timer is reloaded.
  413.             The internal enabled flag is set if either the sweep period or shift are non-zero, cleared otherwise.
  414.             If the sweep shift is non-zero, frequency calculation and the overflow check are performed immediately.
  415.            
  416.           TODO: Some features
  417.         */
  418.       if (!apu->squ_ch[0].length_count) {
  419.         apu->squ_ch[0].length_count = 64;
  420.         if (apu->squ_ch[0].nrx3_x4 & 0x4000) {
  421.           apu->squ_ch[0].signal_phase = 0;
  422.           apu->squ_ch[0].envlope_phase = 0;
  423.         }
  424.       }
  425.       apu->squ_ch[0].nrx3_x4 = value;
  426.       apu->squ_ch[0].signal_volume = apu->squ_ch[0].nrx1_x2 >> 12;
  427.       apu->squ_ch[0].envlope_trigger = 16780000/64 * (apu->squ_ch[0].nrx1_x2 >> 8 & 7);
  428.       apu->squ_ch[0].length_trigger = 16780000/256;
  429.       apu->squ_ch[0].sweep_phase = 0;
  430.     }
  431.     apu->squ_ch[0].signal_trigger =  (int) (  2097500.0  / (131072.0 / (double)(2048 - (value & 2047))) );
  432.     break;
  433.   case 0x06C:
  434.     if (value & 0x8000) {
  435.       apu->settings.nr52 |= 2;
  436.         /*  Trigger Event Same as square 1 */
  437.       if (!apu->squ_ch[1].length_count) {
  438.         apu->squ_ch[1].length_count = 64;
  439.         if (apu->squ_ch[1].nrx3_x4 & 0x4000) {
  440.           apu->squ_ch[1].signal_phase = 0;
  441.           apu->squ_ch[1].envlope_phase = 0;
  442.         }
  443.       }
  444.       apu->squ_ch[1].nrx3_x4 = value;
  445.       apu->squ_ch[1].signal_volume = apu->squ_ch[1].nrx1_x2 >> 12;
  446.       apu->squ_ch[1].envlope_trigger = 16780000/64 * (apu->squ_ch[1].nrx1_x2 >> 8 & 7);
  447.       apu->squ_ch[1].length_trigger = 16780000/256;
  448.       apu->squ_ch[1].sweep_phase = 0;
  449.     }
  450.     apu->squ_ch[1].signal_trigger = (int) (  2097500.0  / (131072.0 / (double)(2048 - (value & 2047))) );
  451.     break;
  452.   case 0x070:
  453.     apu->wave_ch.nr30 = value;
  454.     break;
  455.   case 0x072:
  456.     apu->wave_ch.length_count = 256 - (value & 255);
  457.     apu->wave_ch.length_trigger = 16780000/256;
  458.     apu->wave_ch.nr31_32 = value;
  459.     break;
  460.   case 0x074:
  461.     if (value & 0x80) {
  462.       apu->settings.nr52 |= 4;
  463.       /*  Trigger Event
  464.        *  Writing a value to NR34 with bit 7 set causes the following things to occur:
  465.        *
  466.        *  Channel is enabled (see length counter).
  467.        *  If length counter is zero, it is set to 256.
  468.        *  Frequency timer is reloaded with period.
  469.        *  Wave channel's position is set to 0 but sample buffer is NOT refilled.
  470.        *  Note that if the channel's DAC is off, after the above actions occur the channel will be immediately disabled again.
  471.        *
  472.        *  TODO: Some features
  473.       */
  474.       if (!apu->wave_ch.length_count) {
  475.         apu->wave_ch.length_count = 256;
  476.         if (apu->wave_ch.nr33_34 & 0x4000) {
  477.           apu->wave_ch.output_phase = 0;
  478.         }
  479.       }
  480.       apu->wave_ch.nr33_34 = value;
  481.       apu->wave_ch.length_trigger = 16780000/256;
  482.     }
  483.     apu->wave_ch.output_trigger = (int)((16780000.0/ (131072.0 / (double)(2048 - (value & 2047)))) /
  484.                                                         ((apu->wave_ch.nr30 & 0x20) ? 64.0 : 32.0));
  485.     break;
  486.   case 0x078:
  487.     apu->settings.nr52 |= 8;
  488.     apu->noise_ch.nr41_42 = value;
  489.     apu->noise_ch.signal_volume = value >> 12;
  490.     apu->noise_ch.length_count = 64 - (value & 63);
  491.     apu->noise_ch.length_trigger = 16780000/256;
  492.     apu->noise_ch.envlope_trigger = 16780000/64 * (value >> 8 & 7);
  493.     break;
  494.   case 0x07C:
  495.     if (value & 0x80) {
  496.       apu->settings.nr52 |= 8;
  497.       /*  Trigger Event
  498.        *  Writing a value to NR44 with bit 7 set causes the following things to occur:
  499.        *
  500.        *  Channel is enabled (see length counter).
  501.        *  If length counter is zero, it is set to 64
  502.        *  Frequency timer is reloaded with period.
  503.        *  Volume envelope timer is reloaded with period.
  504.        *  Channel volume is reloaded from NR42.
  505.        *  Noise channel's LFSR bits are all set to 1.
  506.        *  Note that if the channel's DAC is off, after the above actions occur the channel will be immediately disabled again.
  507.       */    
  508.       if (!apu->noise_ch.length_count) {
  509.         apu->noise_ch.length_count = 64;
  510.         if (apu->noise_ch.nr43_44 & 0x4000) {
  511.           apu->noise_ch.signal_phase = 0;
  512.           apu->noise_ch.envlope_phase = 0;
  513.         }
  514.       }
  515.       apu->noise_ch.nr43_44 = value;
  516.       apu->noise_ch.signal_volume = value >> 12;
  517.       apu->noise_ch.length_trigger = 16780000/256;
  518.       apu->noise_ch.envlope_trigger = 16780000/64 * (value >> 8 & 7);
  519.       apu->noise_ch.signal_output = -1;
  520.     } else if ((value ^ apu->noise_ch.nr43_44) & 8) {
  521.       apu->noise_ch.signal_output = -1;
  522.     }
  523.     apu->noise_ch.signal_trigger = (int)(16780000.0/ (524288.0 / (double)(1 << 1 + (value >> 4 & 15))
  524.                                                                / ((value & 7) ? (double) (value & 7) : 0.5  )));
  525.     break;
  526.   case 0x080:
  527.     apu->settings.nr50_51 = value;
  528.     break;
  529.   case 0x082:
  530.     if (value & 0x800) {
  531.       /* Reset FIFO-A */
  532.       apu->fifo_ch[0].count = 0;
  533.       apu->fifo_ch[0].write = 0;
  534.       apu->fifo_ch[0].read = 0;
  535.       memset (apu->fifo_ch[0].buf, 0, sizeof (apu->fifo_ch[0].buf));
  536.     }
  537.     if (value & 0x8000) {
  538.       /* Reset FIFO-B */
  539.       apu->fifo_ch[1].count = 0;
  540.       apu->fifo_ch[1].write = 0;
  541.       apu->fifo_ch[1].read = 0;
  542.       memset (apu->fifo_ch[1].buf, 0, sizeof (apu->fifo_ch[1].buf));
  543.     }
  544.     apu->settings.snd_ctl = value;
  545.     break;
  546.   case 0x084:
  547.     apu->settings.nr52 = (apu->settings.nr52 & 15) | ~(value & 15);
  548.     break;
  549.   case 0x088:
  550.     apu->settings.pwm_ctl = value; /* TODO: pwm control */
  551.     break;
  552.   case 0x090: case 0x0092:
  553.   /* FIFO- A Write */
  554.     apu->fifo_ch[0].buf[apu->fifo_ch[0].write++] = (int8_t) value;
  555.     apu->fifo_ch[0].buf[apu->fifo_ch[0].write++] = (int8_t)(value >> 8);
  556.     apu->fifo_ch[0].count += 2;
  557.     break;
  558.   case 0x094: case 0x096:
  559.   /* FIFO- B Write */
  560.     apu->fifo_ch[1].buf[apu->fifo_ch[1].write++] = (int8_t) value;
  561.     apu->fifo_ch[1].buf[apu->fifo_ch[1].write++] = (int8_t)(value >> 8);
  562.     apu->fifo_ch[1].count += 2;
  563.     break;
  564.   case 0x098: case 0x009A: case 0x09C: case 0x0A0: case 0x0A2: case 0xA4: case 0xA6:
  565.   case 0x09E:
  566.     if (apu->wave_ch.nr30 & 0x40) {
  567.       apu->wave_ch.qram[(addr - 0x098) * 2+0] = value >> 4 & 15;
  568.       apu->wave_ch.qram[(addr - 0x098) * 2+1] = value & 15;
  569.       apu->wave_ch.qram[(addr - 0x098) * 2+2] = value >> 12 & 15;
  570.       apu->wave_ch.qram[(addr - 0x098) * 2+3] = value >> 8 & 15;
  571.     } else {
  572.       apu->wave_ch.qram[(addr - 0x098) * 2+ 32+0] = value >> 4 & 15;
  573.       apu->wave_ch.qram[(addr - 0x098) * 2+ 32+1] = value & 15;
  574.       apu->wave_ch.qram[(addr - 0x098) * 2+ 32+2] = value >> 12 & 15;
  575.       apu->wave_ch.qram[(addr - 0x098) * 2+ 32+3] = value >> 8 & 15;
  576.     }
  577.     apu->wave_ch.xram[((addr - 0x090 & 0x3FF) >> 1) + (apu->wave_ch.nr30 & 0x40) ? 0 : 8] = value;
  578.     break;
  579.   default:
  580.     DEBUG_BREAK ();
  581.   }
  582. }
  583. finline int16_t
  584. adds16 (int16_t u, int16_t v) {
  585.   uint32_t out = (unsigned)u+(unsigned)v;
  586.   if (out > INT16_MAX)
  587.     out = INT16_MAX;
  588.   return (int16_t)out;
  589. }
  590. finline
  591. void apu_mixer_s16 (struct apu *apu, void *volume2) {
  592.   /* Synthesizer- Signed 16bit PCM
  593.     *             Square1 Square2 Wave Noise FIFO-2
  594.     * Amplifier      
  595.     */
  596.   if (!(apu->settings.nr52 & 0x80)) {
  597.     ((int16_t *)volume2)[0] = 0;
  598.     ((int16_t *)volume2)[1] = 1;
  599.   } else {
  600.     int16_t left = 0;
  601.     int16_t right = 0;
  602.     int16_t id;
  603.     int16_t squ_out[2] = { 0, 0};
  604.     int16_t wave_out = 0;
  605.     int16_t noi_out = 0;
  606.     int16_t fifo_out[2];
  607.     /* GBC Sound 4bit -> 16bit
  608.         FIFO Sound 8Bit -> 16Bit */
  609.     /* Square channel - 1, 2*/
  610.     for (id = 0; id!= 2; id++) {
  611.       if (apu->settings.nr52 & (1 << id)) {
  612.         struct channel_squ *squ = & apu->squ_ch[id];
  613.         if (squ->signal_volume != 0)
  614.           squ_out[id] = (int16_t) (squ->duty_vec[squ->duty_poll & 7] ? squ->signal_volume : 0);
  615.         else ;
  616.       }
  617.     }
  618.     /* Wave channel - 3*/
  619.     if (apu->settings.nr52 & 4) {
  620.       struct channel_wave *wave = & apu->wave_ch;
  621.       /* TODO:*/
  622.     }
  623.     /* Noise channel - 4*/
  624.     if (apu->settings.nr52 & 8) {
  625.       struct channel_noise *noi = & apu->noise_ch;
  626.         if (noi->signal_volume != 0)
  627.           noi_out =(int16_t)( (noi->signal_output & 1) ? noi->signal_volume : 0);
  628.         else ;
  629.     }
  630.     /* FIFO channel - 5, 6*/
  631.     for (id = 0; id!= 2; id++) {
  632.       int8_t value = apu->fifo_ch[id].buf[apu->fifo_ch[id].read];
  633.       if (value < 0)
  634.         value = -value;
  635.       fifo_out[id] = value;
  636.     }
  637.     /*Mixer channel */
  638.     if (1) {
  639.       int16_t rcmix_mask = apu->settings.nr50_51 >> 8 & 15;    
  640.       int16_t lcmix_mask = apu->settings.nr50_51 >> 12 & 15;
  641.       int16_t auxi_step = ((apu->settings.snd_ctl & 3) == 2) ? 4 : ((apu->settings.snd_ctl & 1) + 1);
  642.       int16_t lc_step =  (((apu->settings.nr50_51 >> 4  & 7) + 1) * 2184 >> 8) *auxi_step;
  643.       int16_t rc_step = (((apu->settings.nr50_51  & 7) + 1) * 2184 >> 8) *auxi_step;
  644.       /*Mixer right channel */
  645.       if (rcmix_mask & 1)
  646.         right = squ_out[0] * rc_step >> 4;
  647.       if (rcmix_mask & 2)
  648.         right = adds16 (right, squ_out[1] * rc_step >> 4);
  649.       if (rcmix_mask & 4)
  650.         right = adds16 (right, wave_out * rc_step >> 4);
  651.       if (rcmix_mask & 8)
  652.         right = adds16 (right, noi_out * rc_step >> 4);
  653.       if (apu->settings.snd_ctl & 0x100)
  654.         right = adds16 (right, fifo_out[0] << 8 >> (apu->settings.snd_ctl >> 2 & 1 ^ 1));
  655.       if (apu->settings.snd_ctl & 0x1000)
  656.         right = adds16 (right, fifo_out[1] << 8 >> (apu->settings.snd_ctl >> 3 & 1 ^ 1));
  657.       /*Mixer left channel */
  658.       if (lcmix_mask & 1)
  659.         left = squ_out[0] * lc_step >> 4;
  660.       if (lcmix_mask & 2)
  661.         left = adds16 (left, squ_out[1] * lc_step >> 4);
  662.       if (lcmix_mask & 4)
  663.         left = adds16 (left, wave_out * lc_step >> 4);
  664.       if (lcmix_mask & 8)
  665.         left = adds16 (left, noi_out * lc_step >> 4);
  666.       if (apu->settings.snd_ctl & 0x200)
  667.         left = adds16 (left, fifo_out[0] << 8 >> (apu->settings.snd_ctl >> 2 & 1 ^ 1));
  668.       if (apu->settings.snd_ctl & 0x2000)
  669.         left = adds16 (left, fifo_out[1] << 8 >> (apu->settings.snd_ctl >> 3 & 1 ^ 1));
  670.     }
  671.     if (1) {
  672.       static int16_t swi_dir = 0;
  673.       if (swi_dir) {
  674.         ((int16_t *)volume2)[0] = -left;
  675.         ((int16_t *)volume2)[1] = -right;
  676.       } else {
  677.         ((int16_t *)volume2)[0] = left;
  678.         ((int16_t *)volume2)[1] = right;
  679.       }        
  680.       // swi_dir ^= 1;      
  681.     }
  682.   }
  683. }
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