VHDL - Exercicios

-- Sistemas Digitais - BSI 2012/1
-- Prof°: Paulo
-- Tema: VHDL
-- Alunos: Gabriel Ed, Lucas Menezes, Raif Cervany.

-- Projete um contador síncrono crescente módulo 10 usando a abordagem estrutural.
-- O contador deve possuir:
-- * um sinal de clock (CLK) como entrada
-- * quatro sinais de saída, representando a contagem (DCBA).

-- Os seguintes componentes devem formar o contador solicitado:
-- *4 instâncias do componente FF_JK, representando cada FF J-K que compõe o contador, possuíndo todas as entradas J, K, CLR, PRE e CLK devidamente ligadas.
-- *1 instância do componente NAND2, representando a porta NAND de duas entradas que deve ser ligada na entrada CLR de cada FF J-K.
-- *3 instâncias do componente AND4, representando as portas AND de 4 entradas que serão usada para interconectar os FFs.


-- Bibliotecas

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Entidades

-- FF JK

ENTITY FF_JK IS
  PORT (CLK         : IN  std_logic;                -- Clock
        clear       : IN  std_logic;                -- Clear
        pre         : IN std_logic;                 -- preset
        J           : IN std_logic;                 -- J
        K           : IN std_logic;                 -- K
        Q           : OUT std_logic;                -- Saida
        Qb          : OUT std_logic;                -- Saida negada
        )
END FF_JK;

architecture ff_out of FF_JK is
begin
    if rising_edge(CLK) then -- Borda de Subida
    begin processo : process (clear,pre,J,K,Q,Qb)
            if(not(clear)) then Q <= 0; -- Clear
            elsif(not(pre)) then Q <= 1; -- Preset
            else
                if(not(J) and not(K) and Q) then Q <= 1; -- Q0 = 1
                elsif(not(J) and not(K) and not(Q)) then Q <= 0; -- Q0 = 1
                elsif (not(J) and K) then Q <= 0; -- Reset
                elsif (J and not(K)) then Q <= 1; -- Set
                else (J and K) then Q <= not Q; -- Q barra
                end if;
            end if;
        Qb <- not Q;
    end process processo;
    end if;
end ff_out;

-- Porta Nand

ENTITY Nand2 is
    Port (  D,B         : IN std_logic; -- Entradas Lógicas
            N_out       : OUT std_logic;
        )
END Nand2;

architecture Nand2_out of Nand2 is
begin
N_out <= not (D and B);
end Nand2_out;

-- Porta AND

ENTITY And4 is
    Port ( D,C,B,A      : IN std_logic; -- Entradas Lógicas
            S_And       : OUT std_logic; -- Saida Lógica
        )
END And4;

architecture And4_out of And4 is
begin
S_And <= (A and B and C and D);
end And4_out;

-- Circuito final
ENTITY contador IS
  PORT (CLK   : IN  std_logic;                  -- Clock
        D,C,B,A : Out std_logic);               -- Saidas
END contador;

architecture contador_out of contador is
    component FF_JK is
    Port{
        CLK,clear,pre,J,K       : IN  std_logic;                -- Entradas
        Q,Qb                    : OUT std_logic;                -- Saidas
    }
    end component

    component Nand2 is
    Port{
        D,B                 : IN std_logic;                 --Entradas
        S_And                   : Out std_logic;            --Saidas Lógicas
    }
    end component

    component And4 is
    Port{
        D,C,B,A                 : In std_logic;                 --Entradas
        N_out                   : Out std_logic;                --Saidas Lógicas
    }
    end component

    For ALL : FF_JK use entity work.FF_JK(ff_out);
    For ALL : Nand2 use entity work.Nand2(Nand2_out);
    For ALL : And4 use entity work.FF_JK(And4_out);

    signal D_out, C_out, B_out, A_out,nD_out, nC_out, nB_out, nA_out, And1_out, And2_out,And3_out,Nand1_out : std_logic;

begin
    And1 :  And4 port map(1,1,1,A_out,And1_out);  --  POrta And A
    And2 :  And4 port map(1,1,B_out,A_out,And2_out);  --  Porta And AB
    And3 :  And4 port map(1,C_out,B_out,And3_out);  --  Porta And ABC
    Nand1 : Nand2 port map(D_out,B_out,Nand1_out); -- Porta Nand DB - Clear quando contador chegar em 1010 = DB.
    FF_A : FF_JK port map (rising_edge,Nand1_out,1,1,1,A_out,nA_out); -- Valor de A
    FF_B : FF_JK port map (rising_edge,Nand1_out,1,And1_out,And1_out,B_out,nB_out); -- Valor de B
    FF_C : FF_JK port map (rising_edge,Nand1_out,1,And2_out,And2_out,C_out,nC_out); -- Valor de C
    FF_D : FF_JK port map (rising_edge,Nand1_out,1,And3_out,And3_out,D_out,nD_out); -- Valor de D

    begin valores : process (D_out,C_out,B_out,A_out)
    D <= D_out;
    C <= C_out;
    B <= B_out;
    A <= A_out;
    end process valores;
end contador_out;