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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. entity vhd is
  7.     Port (
  8.         clk_i : in std_logic;
  9.         TXD_o : out std_logic := '1';
  10.         RXD_i : in std_logic
  11.         );
  12. end vhd;
  13.  
  14. architecture Behavioral of vhd is
  15. signal data : std_logic_vector(7 downto 0) := "00000000";
  16. begin
  17. process (clk_i)
  18.  
  19. variable counter : integer range 0 to 5208 := 0;
  20. variable index : integer range -1 to 8 := 0;
  21. variable receive : boolean := false;
  22. variable send : boolean := false;
  23. variable half : boolean := false;
  24.  
  25. begin
  26.  
  27. if rising_edge(clk_i) then
  28.     counter := counter + 1;
  29.    
  30.     if (receive = false and RXD_i = '0') then
  31.         counter := 0;
  32.         index := 0;
  33.         receive := true;
  34.     end if;
  35.    
  36.     if (receive = true and half = false and counter > 2000 and counter < 3000) then
  37.         half := true;
  38.         counter := 0;
  39.     end if;
  40.  
  41.     if (receive = true) then
  42.         if (counter = 5208 and index < 8) then
  43.             data(index) <= RXD_i;
  44.             counter := 0;
  45.             index := index + 1;
  46.         elsif (counter = 5208 and index = 8 and RXD_i = '1') then
  47.             counter := 0;
  48.             index := -1;
  49.             send := true;
  50.             receive := false;
  51.             --data <= data + x"20";
  52.             half := false;
  53.         elsif (counter = 5208 and index = 8 and RXD_i /= '1') then
  54.             counter := 0;
  55.             index := 0;
  56.             receive := false;
  57.         end if;
  58.     end if;
  59.  
  60.     if (send = true) then
  61.         if(index = -1) then
  62.             TXD_o <= '0';
  63.             index := index + 1;
  64.             counter := 0;
  65.         elsif(counter = 5208 and index < 8 and index > -1) then
  66.             TXD_o <= data(index);
  67.             counter := 0;
  68.             index := index + 1;
  69.         elsif (counter = 5208 and index = 8) then
  70.             TXD_o <= '1';
  71.             counter := 0;
  72.             index := 0;
  73.             send := false;
  74.         end if;
  75.     end if;
  76.  
  77. end if;
  78. end process;
  79. end Behavioral;
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