reset_logic

--------- reset_logic -----------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reset_logic is
port(
    reset_in        : in std_logic;
    hrs_bin1        : in std_logic_vector(3 downto 0);
    hrs_bin10       : in std_logic_vector(3 downto 0);
    reset_out       : out std_logic);
end reset_logic;

architecture structural of reset_logic is

begin

    reset_process: process(reset_in)
    begin       -- reset ved aktivering af reset_in eller ved højere end 24 timer
        if ((reset_in = '0') or ((hrs_bin1 = "0100") and hrs_bin10 = "0010")) then
            reset_out <= '0';
        else
            reset_out <= '1';
        end if;
    end process;

end structural;