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Nov 18th, 2019
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VHDL 0.30 KB | None | 0 0
  1. library ieee;
  2.  
  3. use ieee.std_logic_1164.all;
  4.  
  5. entity KombMreze is
  6.     port(
  7.     iSW : in std_logic_vector (7 downto 0);
  8.     iINV : in std_logic;
  9.    
  10.     oLED : out std_logic_vector (7 downto 0);
  11.     oSIGN : out std_logic;
  12.     oGREAT : out std_logic
  13.     );
  14. end entity;
  15.  
  16. architecture Behavioral of KombMreze is
  17. begin
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