uart_interface

LIBRARY ieee;
use ieee.numeric_std.all;
use IEEE.std_logic_1164.all;

ENTITY uart_interface IS
    generic (
            g_CLKS_PER_BIT : integer     -- fpga clock freq / baudrate = 133E6/115200 ~= 1155
        );
    PORT(
            rst                     :   in  std_logic;
            clk                     :   in  std_logic;

            rx_serial               :   in  std_logic;

            ready                   :   out std_logic;

            byte0                   :   out std_logic_vector(7 downto 0);
            byte1                   :   out std_logic_vector(7 downto 0);
            byte2                   :   out std_logic_vector(7 downto 0);
            byte3                   :   out std_logic_vector(7 downto 0);
            byte4                   :   out std_logic_vector(7 downto 0);
            byte5                   :   out std_logic_vector(7 downto 0)
        );
END ENTITY uart_interface;

ARCHITECTURE behavioural OF uart_interface IS
    component uart_receiver
        generic (
            g_CLKS_PER_BIT : integer     -- fpga clock freq / baudrate = 133E6/115200 ~= 1155
        );

            port (
        rst         : in    std_logic;
        clk         : in    std_logic; -- fpga clock
        rx_serial   : in    std_logic; -- RX signal coming from the serial-communication cable

        rx_dv       : out   std_logic; -- data valid signal
        rx_byte     : out   std_logic_vector(7 downto 0) -- 8 bit data
        );
    end component;

    component uart_byte_collector
        PORT(
            rst                     :   in  std_logic;
            clk                     :   in  std_logic;

            rx_dv                   :   in  std_logic;
            rx_byte                 :   in  std_logic_vector(7 downto 0);

            ready                   :   out std_logic;

            byte0                   :   out std_logic_vector(7 downto 0);
            byte1                   :   out std_logic_vector(7 downto 0);
            byte2                   :   out std_logic_vector(7 downto 0);
            byte3                   :   out std_logic_vector(7 downto 0);
            byte4                   :   out std_logic_vector(7 downto 0);
            byte5                   :   out std_logic_vector(7 downto 0)
        );
    end component;

    signal rx_dv : std_logic;
    signal rx_byte : std_logic_vector(7 downto 0);

begin


    inst_uart_receiver : uart_receiver      generic map (
                                                            g_CLKS_PER_BIT => g_CLKS_PER_BIT
                                                    )
                                            port map (
                                                            rst => rst,
                                                            clk => clk,
                                                            rx_serial => rx_serial,
                                                            rx_dv => rx_dv,
                                                            rx_byte => rx_byte
                                                    );

    inst_uart_byte_collector : uart_byte_collector
                                            port map (
                                                                    rst => rst,
                                                                    clk => clk,
                                                                    rx_dv => rx_dv,
                                                                    rx_byte => rx_byte,

                                                                    ready => ready,

                                                                    byte0 => byte0,
                                                                    byte1 => byte1,
                                                                    byte2 => byte2,
                                                                    byte3 => byte3,
                                                                    byte4 => byte4,
                                                                    byte5 => byte5
                                                                    );

end architecture behavioural;