count_ones_tester

--------- count_ones_tester ---------
Library ieee;
use ieee.std_logic_1164.all;

entity count_ones_tester is
port(
    SW      : in std_logic_vector(7 downto 0);
    HEX0    : out std_logic_vector(6 downto 0);
    HEX1    : out std_logic_vector(6 downto 0);
    HEX2    : out std_logic_vector(6 downto 0);
    HEX3    : out std_logic_vector(6 downto 0);
    HEX4    : out std_logic_vector(6 downto 0);
    HEX5    : out std_logic_vector(6 downto 0);
    HEX6    : out std_logic_vector(6 downto 0);
    HEX7    : out std_logic_vector(6 downto 0));
end count_ones_tester;

architecture structural of count_ones_tester is
    signal onesBin : std_logic_vector(3 downto 0);

begin
I1: entity work.count_ones
    port map(
        A       => SW,
        ones    => onesBin);

I2: entity work.bin2hex
    port map(
        bin     => onesBin,
        seg     => HEX0);

        -- Vi slukker alle HEX displays som ikke er i brug; bare for at gøre spillet pænere.
        HEX1    <= "1111111";
        HEX2    <= "1111111";
        HEX3    <= "1111111";
        HEX4    <= "1111111";
        HEX5    <= "1111111";
        HEX6    <= "1111111";
        HEX7    <= "1111111";
end structural;