library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity SPI is
port(

        data_out: out STD_LOGIC_VECTOR(7 downto 0);
      data_in: in STD_LOGIC_VECTOR(7 downto 0);
        address: in STD_LOGIC_VECTOR(2 downto 0);

        en: in STD_LOGIC;
        wr_en: in STD_LOGIC;


        mclk: in STD_LOGIC;
        sclk: out STD_LOGIC;
        ss_out: out STD_LOGIC;
        ss_in: in STD_LOGIC;
        spi_out: out STD_LOGIC;
        spi_in: out STD_LOGIC


);
end SPI;

architecture zachowanie of SPI is

signal dzielnik : unsigned(1 downto 0);
signal bit_counter : unsigned(2 downto 0) := b"000";
signal f_sclk_signal : STD_LOGIC;
signal busy: STD_LOGIC;
signal state: STD_LOGIC := '0';
signal address_reg: STD_LOGIC_VECTOR(2 downto 0):= "000";
signal status_reg : STD_LOGIC_VECTOR(7 downto 0):= "00000000";
signal conf_reg : STD_LOGIC_VECTOR(7 downto 0):= "00000000";
signal shift_reg : STD_LOGIC_VECTOR(7 downto 0):= "00000000";


begin


process(state) begin
if(rising_edge(state)) then




end if;
end process;


process(shift_reg) begin
status_reg(0)<='1';
end process;

process(mclk) begin
if(rising_edge(mclk)) then

if (state = '0') then
if en = '1' and wr_en = '1' then
address_reg <=address;
state<='1';
end if;

else
state <= '0';
case address_reg is
when "00" => if(status_reg(0) = '0') then shift_reg(7 downto 0)<=data_in(7 downto 0); end if;
when "01" => status_reg(7 downto 0)<=data_in(7 downto 0);
when "10" => conf_reg(7 downto 0)<=data_in(7 downto 0);
end case;

end if;

end if;
end process;



process(mclk) begin
if(rising_edge(mclk)) then
    if(dzielnik = b"11") then
    dzielnik <= b"00";
    else
    dzielnik <= dzielnik + 1;
    end if;
end if;

end process;



process(f_sclk_signal) begin
if(falling_edge(f_sclk_signal) and status_reg(0) = '1') then
    if(bit_counter = 7) then
    bit_counter <= b"000";
    status_reg(0) <= '0';
    else

    shift_reg(7 downto 1)<= shift_reg(6 downto 0);
    bit_counter <= bit_counter + 1;
    end if;
end if;
end process;





spi_out<=shift_reg(23);
sclk<=not dzielnik(1);
f_sclk_signal<=not dzielnik(1);
end zachowanie;