library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SIMPLE_SRAM_CONTROLLER is

    port
    (
            CLK         :   in  std_logic;
            RESET           :   in  std_logic:='1';
            RnW         :   in std_logic:='1';
            ADDR        :   in unsigned(15 downto 0);
            DATA_BUS        :   INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
            SRAM_ADDR   :   OUT std_logic_vector(16 downto 0) := "00000000000000000";
            SRAM_DATA   :   INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
            SRAM_BANKS  :   BUFFER std_logic_vector(7 downto 0):="00000000";
            SRAM_CS     :   BUFFER std_logic:='1'
    );

end entity;

architecture behavioral of SIMPLE_SRAM_CONTROLLER is
--signal CACHE  :   std_logic_vector(7 downto 0);

begin
SRAM_ADDR(13 downto 0) <= std_logic_vector(ADDR(13 downto 0));
SRAM_ADDR(16 downto 14) <= SRAM_BANKS(2 downto 0);



decode:process(RESET,CLK)
begin
if RESET = '0' then
    SRAM_CS <= '1';
    SRAM_BANKS<="00000000";
else
    if to_integer(ADDR(15 downto 0)) = 16#CE00# then
        if RnW = '0' then
            SRAM_BANKS <= DATA_BUS;
            --CACHE <= DATA_BUS;
        else
            DATA_BUS <= SRAM_BANKS;
        end if;
    else
        if to_integer(ADDR(15 downto 12)) >= 16#8# AND to_integer(ADDR(15 downto 12)) <= 16#B# then
            SRAM_CS <= '0';

            if RnW = '0' then
                DATA_BUS <= "ZZZZZZZZ";
                SRAM_DATA <= DATA_BUS;
            else
                DATA_BUS <= SRAM_DATA;
            end if;
        else
            SRAM_CS <= '1';
            SRAM_DATA <= "ZZZZZZZZ";
            DATA_BUS <= "ZZZZZZZZ";
        end if;
    end if;

end if;
end process;

end behavioral;