adolf01

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Jun 17th, 2020
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity SIMPLE_SRAM_CONTROLLER is
  6.  
  7.     port
  8.     (
  9.             CLK         :   in  std_logic;
  10.             RESET           :   in  std_logic:='1';
  11.             RnW         :   in std_logic:='1';
  12.             ADDR        :   in unsigned(15 downto 0);
  13.             DATA_BUS        :   INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
  14.             SRAM_ADDR   :   OUT std_logic_vector(16 downto 0) := "00000000000000000";
  15.             SRAM_DATA   :   INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
  16.             SRAM_BANKS  :   BUFFER std_logic_vector(7 downto 0):="00000000";
  17.             SRAM_CS     :   BUFFER std_logic:='1'
  18.     );
  19.  
  20. end entity;
  21.  
  22. architecture behavioral of SIMPLE_SRAM_CONTROLLER is
  23. --signal CACHE  :   std_logic_vector(7 downto 0);
  24.  
  25. begin
  26. SRAM_ADDR(13 downto 0) <= std_logic_vector(ADDR(13 downto 0));
  27. SRAM_ADDR(16 downto 14) <= SRAM_BANKS(2 downto 0);
  28.  
  29.  
  30.  
  31. decode:process(RESET,CLK)
  32. begin
  33. if RESET = '0' then
  34.     SRAM_CS <= '1';
  35.     SRAM_BANKS<="00000000";
  36. else
  37.     if to_integer(ADDR(15 downto 0)) = 16#CE00# then
  38.         if RnW = '0' then
  39.             SRAM_BANKS <= DATA_BUS;
  40.             --CACHE <= DATA_BUS;
  41.         else
  42.             DATA_BUS <= SRAM_BANKS;
  43.         end if;
  44.     else
  45.         if to_integer(ADDR(15 downto 12)) >= 16#8# AND to_integer(ADDR(15 downto 12)) <= 16#B# then
  46.             SRAM_CS <= '0';
  47.            
  48.             if RnW = '0' then
  49.                 DATA_BUS <= "ZZZZZZZZ";
  50.                 SRAM_DATA <= DATA_BUS;
  51.             else
  52.                 DATA_BUS <= SRAM_DATA;
  53.             end if;
  54.         else
  55.             SRAM_CS <= '1';
  56.             SRAM_DATA <= "ZZZZZZZZ";
  57.             DATA_BUS <= "ZZZZZZZZ";
  58.         end if;
  59.     end if;
  60.  
  61. end if;
  62. end process;
  63.  
  64. end behavioral;
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