felixen98

Test

Feb 18th, 2019
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VHDL 4.01 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.all;
  4.  
  5.  
  6. entity lab is
  7.     Port ( clk,rst, rx : in  STD_LOGIC;    -- rst är tryckknappen i mitten under displayen
  8.            seg: out  UNSIGNED(7 downto 0);
  9.            an : out  UNSIGNED (3 downto 0));
  10. end lab;
  11.  
  12. architecture Behavioral of lab is
  13.  
  14.   component leddriver
  15.     Port ( clk,rst : in  STD_LOGIC;
  16.            seg : out  UNSIGNED(7 downto 0);
  17.            an : out  UNSIGNED (3 downto 0);
  18.            value : in  UNSIGNED (15 downto 0));
  19.   end component;
  20.  
  21.     signal sreg : UNSIGNED(9 downto 0) := B"0_00000000_0";  -- 10 bit skiftregister
  22.     signal tal : UNSIGNED(15 downto 0) := X"0000";
  23.     signal rx1,rx2 : std_logic;         -- vippor på insignalen
  24.     signal sp : std_logic;              -- skiftpuls
  25.     signal run : std_logic;             -- Bestäm om vi ska läsa in ett värde eller inte
  26.     signal lp : std_logic;              -- laddpuls
  27.     signal pos : UNSIGNED(1 downto 0) := "00";
  28.     signal bit_counter : UNSIGNED(9 downto 0) := "0000000000";
  29.     signal state_counter : UNSIGNED(3 downto 0) := "0000";
  30.     alias nya_talet: unsigned(3 downto 0) sreg(3 downto 0);
  31.     alias pos0: unsigned(3 downto 0) tal(15 downto 12);
  32.     alias pos1: unsigned(3 downto 0) sreg(11 downto 8);
  33.     alias pos2: unsigned(3 downto 0) sreg(7 downto 4);
  34.     alias pos3: unsigned(3 downto 0) sreg(3 downto 0);
  35.  
  36. // vippor
  37. begin
  38.   process(clk) begin
  39.     if rising_edge(clk) then
  40.       if rst = '1' then
  41.         rx1 <= '1';
  42.         rx2 <= '1';
  43.       else
  44.         rx1 <= rx;
  45.         rx2 <= rx1;
  46.       end if;
  47.     end if;
  48.   end process;
  49.    
  50. // skiftregister
  51.   process(clk) begin
  52.     if rising_edge(clk) then
  53.       if rst = '1' then
  54.         sreg <= "0000000000";
  55.       elsif sp = '1' then
  56.         sreg <= sreg + rx2;
  57.         sreg <= sreg ror 1;
  58.       else then
  59.         sreg <= sreg;
  60.     end if;
  61.   end process;
  62.  
  63.  
  64. // styrenhet
  65.   process(clk) begin
  66.     if rising_edge(clk) then
  67.       if rst = '1' then
  68.         bit_counter <= "0000000000";
  69.         state_counter <= "0000";
  70.         run <= '0';
  71.         lp <= '0';
  72.         sp <= '0';
  73.       elsif run = '1' then
  74.         sp <= '0';
  75.         lp <= '0';
  76.         bit_counter <= bit_counter + '1';
  77.         if bit_counter = "110110010" and state_counter = '0' then -- Läs första biten
  78.           sp <= '1';
  79.           bit_counter <= "0000000000";
  80.           state_counter <= state_counter + '1';
  81.         elsif bit_counter = "1101100100" then // Läs nästa bit
  82.           sp <= '1';
  83.           bit_counter <= "0000000000";
  84.           state_counter <= state_counter + '1';
  85.         elsif bit_counter = "110110010" and state_counter = "1001" then
  86.           lp <= '1';
  87.           bit_counter <= "0000000000";
  88.           state_counter <= "0000";
  89.         else then
  90.           bit_counter <= bit_counter;
  91.         end if;
  92.       elsif rx1 = '0' and rx2 = '1' then
  93.         run <= '1';
  94.         bit_counter <= bit_counter + 1;
  95.       else then
  96.         run <= run;
  97.       end if;
  98.     end if;
  99.   end process;
  100.  
  101.  
  102.  
  103.  
  104. // 2-bitsräknare
  105.  
  106.   process(clk) begin
  107.     if rising_edge(clk) then
  108.       if rst = '1' then
  109.         pos <= "00";
  110.       elsif pos = "11" then
  111.         pos <= "00";
  112.       elsif lp = '1' then
  113.         pos <= pos + 1;
  114.       else then
  115.         pos <= pos;
  116.       end if;
  117.     end if;
  118.   end process;
  119.  
  120.  
  121.  
  122. // 16- bitsregister
  123.  
  124.   process(clk) begin
  125.     if rising_edge(clk) then
  126.       if rst = '1' then
  127.         pos0 <= "0000";
  128.         pos1 <= "0000";
  129.         pos2 <= "0000";
  130.         pos3 <= "0000";
  131.       elsif pos = "00" then
  132.         pos0 <= nya_talet;
  133.       elsif pos = "01" then
  134.         pos1 <= nya_talet;
  135.       elsif pos = "10" then
  136.         pos2 <= nya_talet;
  137.       elsif pos = "11" then
  138.         pos3 <= nya_talet;
  139.       else then
  140.         pos0 <= pos0;
  141.       end if;
  142.     end if;
  143.   end process;
  144.  
  145.  
  146.   -- *****************************
  147.   -- * Multiplexad display       *
  148.   -- *****************************
  149.   -- Inkoppling av komponenten leddriver
  150.   led: leddriver port map (clk, rst, seg, an, tal);
  151.  
  152. end Behavioral;
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