library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;



entity dc_gray is

  port

  ( b_in      : in std_logic_vector (3 downto 0); --:= "1010";



    b_out      : out std_logic_vector (3 downto 0)

  );

end dc_gray;









ARCHITECTURE behv OF dc_gray IS



BEGIN



    b_out <= "0000" WHEN b_in = "0000" ELSE



           "0001" WHEN b_in = "0001" ELSE



           "0010" WHEN b_in = "0011" ELSE



           "0011" WHEN b_in = "0010" ELSE



           "0100" WHEN b_in = "0110" ELSE



           "0101" WHEN b_in = "0111" ELSE



           "0110" WHEN b_in = "0101" ELSE



           "0111" WHEN b_in = "0100" ELSE



           "1000" WHEN b_in = "1100" ELSE



           "1001" WHEN b_in = "1101" ELSE



           "1010" WHEN b_in = "1111" ELSE



           "1011" WHEN b_in = "1110" ELSE



           "1100" WHEN b_in = "1010" ELSE



           "1101" WHEN b_in = "1011" ELSE



           "1110" WHEN b_in = "1001" ELSE



           "1111" WHEN b_in = "1000" ELSE



           "0000";



END behv;