20141212_Verilog_ShiftRegister

/***************************************/
/** 20141211 Shift Register           **/
/** Maker  : Yan                      **/
/** E-Mail : [email protected] **/
/** Date   : 2014/12/12 am.00:00      **/
/***************************************/

/* Set port
   Clk      = PIN_Y2 (Is 50MHz)
   Clr      = PIN_M23
   Trigger  = PIN_M21
   out[8:0] = PIN_F17
          PIN_G21
          PIN_G22
          PIN_G20
          PIN_H21
          PIN_E24
          PIN_E25
          PIN_E22
          PIN_E21       */

module ShiftRegister(Clk, Trigger, Clr, Out);
    input       Clk, Trigger, Clr;
    output reg  [8:0] Out;

    //A customize divider
    wire    o_Clk;
    divn #(.WIDTH(30),
           .N(5000000)) tmp(.Clk(Clk), .rst_n(Clr), .o_Clk(o_Clk));

    /*Set a variable to remember Style(Right-Move or Left-Move)
      If(tmp_style == 0)
            It's will be a Right-Shift Regedit.
      Else If(tmp_style == 1)
            It's will be a Right-Shift Regedit. */
    reg tmp_style = 0;
    reg [8:0]   tmp_out;

    //Trigger Style
    always@(negedge Trigger)
    begin
        if(Trigger == 0)
            tmp_style = ~tmp_style;
    end

    //Move
    always@(posedge o_Clk or negedge Clr)
    begin :f //ifhave a variable declaration in always, you should key in this
        integer i; //For [For] to use
        if(Clr == 0)
            tmp_out = 9'b111111110;
        else
            if(o_Clk == 1)
                if(tmp_style == 0)
                    if(tmp_out == 9'b011111111)
                        tmp_out = 9'b111111110;
                    else
                    begin
                        for(i = 8; i > 0; i = i - 1)
                            tmp_out[i] = tmp_out[i - 1];
                        tmp_out[0] = 1;
                    end
                else if(tmp_style == 1)
                    if(tmp_out == 9'b111111110)
                        tmp_out = 9'b011111111;
                    else
                    begin
                        for(i = 0; i < 8; i = i + 1)
                            tmp_out[i] = tmp_out[i + 1];
                        tmp_out[8] = 1;
                    end
        Out = tmp_out; //To transmit the value to output port(Out)
    end
endmodule

//A Mod N Divider
module divn(Clk, rst_n, o_Clk);
    input   Clk, rst_n;
    output  o_Clk;
    parameter WIDTH = 3; //Register long
    parameter N     = 6; //A number which you want to mod

    reg [WIDTH - 1:0]   cnt_p;
    reg [WIDTH - 1:0]   cnt_n;
    reg         Clk_p;
    reg         Clk_n;

    assign o_Clk = (N == 1) ? Clk :
               (N[0])   ? (Clk_p | Clk_n) : (Clk_p); //N[0] is use for judge N is or not a odd number

    always@(posedge Clk or negedge rst_n)
    begin
      if(!rst_n)
         cnt_p <= 0;
      else if(cnt_p == (N - 1))
         cnt_p <= 0;
      else
         cnt_p <= cnt_p + 1;
    end

    always@(posedge Clk or negedge rst_n)
    begin
      if(!rst_n)
         Clk_p <= 1;
      else if(cnt_p < (N >> 1)) //(N >> 1) is the same as (N / 2)
         Clk_p = 1;
      else
         Clk_p = 0;
    end

    always@(negedge Clk or negedge rst_n)
    begin
      if(!rst_n)
         cnt_n <= 0;
      else if(cnt_n == (N - 1))
         cnt_n <= 0;
      else
         cnt_n <= cnt_n + 1;
    end

    always@(negedge Clk or negedge rst_n)
    begin
      if(!rst_n)
         Clk_n <= 1;
      else if(cnt_n < (N >> 1))
         Clk_n = 1;
      else
         Clk_n = 0;
    end
endmodule