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Nov 12th, 2018
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VHDL 0.71 KB | None | 0 0
  1.  
  2. entity DomaciZadatak2 is
  3.     Port ( iSEL : in  STD_LOGIC;
  4.            iSW : in  STD_LOGIC_VECTOR (7 downto 0);
  5.            oLED : out  STD_LOGIC_VECTOR (7 downto 0));
  6. end DomaciZadatak2;
  7.  
  8. architecture Behavioral of DomaciZadatak2 is
  9.  
  10. begin
  11.     process (iSEL,iSW) begin
  12.         case(iSEL) is
  13.             when '0' =>
  14.                 oLED <= not(iSW);
  15.             when '1' =>
  16.                 oLED(3 downto 0) <= iSW(7 downto 4) - iSW(3 downto 0);
  17.                 if( iSW(7 downto 4) > iSW(3 downto 0)) then
  18.                     oLED(4) <= '0';
  19.                 else
  20.                     oLED(4) <= '1';
  21.                 end if;
  22. --              dis dont work
  23. --              not(iSW + "1") and
  24.                 oLED(7 downto 5) <= (not(iSW + "1") and iSW);
  25.                
  26.                 when others =>
  27.                 oLED <= (others => '1');
  28.         end case;
  29.  
  30.     end process;
  31.  
  32. end Behavioral;
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