Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- entity DomaciZadatak2 is
- Port ( iSEL : in STD_LOGIC;
- iSW : in STD_LOGIC_VECTOR (7 downto 0);
- oLED : out STD_LOGIC_VECTOR (7 downto 0));
- end DomaciZadatak2;
- architecture Behavioral of DomaciZadatak2 is
- begin
- process (iSEL,iSW) begin
- case(iSEL) is
- when '0' =>
- oLED <= not(iSW);
- when '1' =>
- oLED(3 downto 0) <= iSW(7 downto 4) - iSW(3 downto 0);
- if( iSW(7 downto 4) > iSW(3 downto 0)) then
- oLED(4) <= '0';
- else
- oLED(4) <= '1';
- end if;
- -- dis dont work
- -- not(iSW + "1") and
- oLED(7 downto 5) <= (not(iSW + "1") and iSW);
- when others =>
- oLED <= (others => '1');
- end case;
- end process;
- end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement