MUX 2 TO 1

-- design.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity mux2to1 is
    port(A : in bit_vector(1 downto 0);
         Sel : in std_logic_vector(1 downto 0);
         F : out bit);
end entity;

architecture mux2to1_arch of mux2to1 is
begin
    process(A, Sel)
    begin
        if(Sel = "01") then
            F <= A(0);
        elsif(Sel = "10") then
            F <= A(1);
        else
            F <= '0';
        end if;
    end process;
end architecture mux2to1_arch;

-- testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity mux2to1_tb is
end entity mux2to1_tb;

architecture mux2to1_tb_arch of mux2to1_tb is
    signal A : bit_vector(1 downto 0);
    signal Sel : std_logic_vector(1 downto 0);
    signal F : bit;
begin
    DUT1 : entity work.mux2to1(mux2to1_arch)
           port map(A, Sel, F);
    STIMULUS : process
    begin
        A <= "01"; wait for 10ns;
        Sel <= "00"; wait for 10ns;
        Sel <= "01"; wait for 10ns;
        Sel <= "10"; wait for 10ns;
        Sel <= "11"; wait for 10ns;
        Sel <= "XX"; wait for 10ns;
    end process STIMULUS;
end architecture mux2to1_tb_arch;