library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity part2 is
 PORT( clk, rd, we: in std_logic;
        addr: in std_logic_vector(1 downto 0);
        data_in: in std_logic_vector(7 downto 0);
        data_out: out std_logic_vector(7 downto 0));
 end;

Architecture arch of part2 is
Type my_array is array (0 to 3) of std_logic_vector(7 downto 0);
signal ram: my_array;
signal rw: std_logic_vector(1 downto 0);
Begin
rw<= rd & we;

    Process(clk)
        Begin
            if (clk 'event and clk ='1') then
            case rw is
            when "01" => ram(to_integer(unsigned(addr))) <= data_in;
            when "10" => data_out <= ram (to_integer (unsigned (addr)));
            when others => data_out <= "ZZZZZZZZ";
            end case;
            end if;
            end process;
            end arch;