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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    09:48:09 03/20/2019
  6. -- Design Name:
  7. -- Module Name:    display - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21.  
  22. use IEEE.std_logic_1164.all;
  23. use IEEE.numeric_std.all;
  24. use IEEE.std_logic_unsigned.all;
  25.  
  26. -- Uncomment the following library declaration if using
  27. -- arithmetic functions with Signed or Unsigned values
  28. --use IEEE.NUMERIC_STD.ALL;
  29.  
  30. -- Uncomment the following library declaration if instantiating
  31. -- any Xilinx primitives in this code.
  32. --library UNISIM;
  33. --use UNISIM.VComponents.all;
  34.  
  35. entity display is
  36.     Port ( anoda : out  STD_LOGIC_VECTOR (3 downto 0);
  37.            LDisplay : out  STD_LOGIC_VECTOR (6 downto 0);
  38.               jed, dzi, set, tys : in  STD_LOGIC_VECTOR (3 downto 0);
  39.            clock : in  STD_LOGIC);
  40. end display;
  41.  
  42. architecture Behavioral of display is
  43.  
  44. signal mux: STD_LOGIC_VECTOR (3 downto 0);
  45. signal clk_200Hz :std_logic;
  46. signal zlicz : std_logic_vector (1 downto 0);
  47.  
  48. begin
  49.  
  50. process (clk_200Hz)
  51. begin
  52.    if ( clk_200Hz'event and clk_200Hz = '1') then
  53.       zlicz <= zlicz + 1;
  54.    end if;
  55. end process;
  56.  
  57. process (clock)
  58.     variable temp: natural range 0 to 50000000;
  59. begin  
  60.  
  61.    if (clock'event and clock = '1') then
  62.       temp :=temp+1;
  63.         if temp = 20000 then
  64.             temp:=0;
  65.             clk_200Hz <= not clk_200Hz;
  66.         end if;
  67.    end if;
  68. end process;
  69.  
  70.  
  71. With zlicz Select
  72. anoda <= not "0001" when "00",
  73.             not "0010" when "01",
  74.             not "0100" when "10",
  75.             not "1000" when "11";
  76.            
  77. with zlicz Select
  78. mux <=  jed when "00",
  79.             dzi when "01",
  80.             set when "10",
  81.             tys when "11";
  82.            
  83.  
  84. With mux Select
  85. LDisplay <= NOT "1111110" when "0000",
  86.                 NOT "0110000" when "0001",
  87.                 NOT "1101101" when "0010",
  88.                 NOT "1111001" when "0011",
  89.                 NOT "0110011" when "0100",
  90.                 NOT "1011011" when "0101",
  91.                 NOT "1011111" when "0110",
  92.                 NOT "1110000" when "0111",
  93.                 NOT "1111111" when "1000",
  94.                 NOT "1111011" when "1001",
  95.                 NOT "1110111" when "1010",
  96.                 NOT "0011111" when "1011",
  97.                 NOT "1001110" when "1100",
  98.                 NOT "0111101" when "1101",
  99.                 NOT "1001111" when "1110",
  100.                 NOT "1000111" when "1111";
  101.  
  102.  
  103. end Behavioral;
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