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ROM from RAM code

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Jun 5th, 2018
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VHDL 0.79 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4.  
  5. entity rom is
  6. generic(
  7.     address_length: natural := 2;
  8.     data_length: natural := 4
  9. );
  10. port(
  11.     clock: in std_logic;
  12.     rom_enable: in std_logic;
  13.     address: in std_logic_vector((address_length - 1) downto 0);
  14.     data_output: out std_logic_vector ((data_length - 1) downto 0)
  15. );
  16. end rom;
  17.  
  18. architecture arch of rom is
  19.     type rom_type is array (0 to (2**(address_length) -1)) of std_logic_vector((data_length - 1) downto 0);
  20.    
  21.     -- set the data on each adress to some value)
  22.     constant mem: rom_type:=
  23.     (
  24.         "1001",
  25.         "0110",
  26.         "0000",
  27.         "1111"
  28.     );
  29. begin
  30.  
  31. process(clock) is
  32. begin
  33.     if(rising_edge(clock) and rom_enable = '1') then
  34.         data_output <= mem(conv_integer(unsigned(address)));
  35.     end if;
  36. end process;
  37.  
  38. end arch;
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