library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity eq_calculator is
    port (data_in : in signed (7 downto 0);
            clk, addfilter_sub_h, regfilter_rst_h, mux2to1_sign_h, mux2to1_maxmin, mux2to1_v_h : in std_logic;
            mux4to1_sel : in std_logic_vector (1 downto 0);
            add_v_h, msb_sum : out std_logic;
            data_out : out signed (7 downto 0));
    end eq_calculator;

architecture behavior of eq_calculator is

component F_adder is
    generic (N: integer :=10);
    port (x, y : in signed (N-1 downto 0);
            sub   : in std_logic;
            S    : out signed (N-1 downto 0));
end component;

component generic_mux2to1 IS
    GENERIC ( N : POSITIVE := 8) ;
    PORT ( w0, w1  : IN STD_LOGIC_VECTOR( ( N - 1 ) DOWNTO 0 ) ;
                  s         :   IN STD_LOGIC ;
                  f        :     OUT STD_LOGIC_VECTOR( ( N - 1 ) DOWNTO 0 ) ) ;
END component;

component mux4to1 IS
    GENERIC ( N : POSITIVE := 10) ;
    PORT ( w0, w1, w2, w3  :      IN STD_LOGIC_VECTOR( ( N - 1 ) DOWNTO 0 ) ;
                  s           :       IN STD_LOGIC_VECTOR (1  DOWNTO 0) ;
                  f           :     OUT STD_LOGIC_VECTOR( ( N - 1 ) DOWNTO 0 ) ) ;
END component;

COMPONENT regist IS
 GENERIC ( N : integer:=10);
 PORT (R                : IN SIGNED(N-1 DOWNTO 0);
         Clock, Resetn, Enable : IN STD_LOGIC;
         Q              : OUT SIGNED(N-1 DOWNTO 0));
END COMPONENT;

signal mux_n_1, mux_n, mux_n_3, sum, reg_sum : signed (9 downto 0);
signal A, B : std_logic_vector (9 downto 0);
signal maxmin,d_out : std_logic_vector (7 downto 0);

begin

    mux_n_1 <= data_in(7) & data_in(7) & data_in; -- data in 10 bit
    mux_n   <= data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7 downto 2); -- data in 10 bit divided by 4
    mux_n_3 <= data_in(7)& data_in & '0'; -- data in 10 bit multiplied by 2

    muxB_select: mux4to1 port map (w0 => std_logic_vector(mux_n_1), w1 => std_logic_vector(mux_n), w2 => std_logic_vector(mux_n_3), w3 => std_logic_vector(reg_sum), s => mux4to1_sel, f => B);
    muxA_select: generic_mux2to1 generic map (N => 10)
                                 port map (w0 => std_logic_vector(reg_sum), w1 => (others => '0'), s => mux2to1_sign_h, f => A);

    adder        : F_adder port map (x => signed(A), y => signed(B), sub => addfilter_sub_h, S => sum);
    sum_regist: regist port map (R => sum, Clock => clk, Resetn => regfilter_rst_h, Enable => '1', Q => reg_sum);

    add_v_h <= (reg_sum(9) xor reg_sum(8)) or (reg_sum(9) xor reg_sum(7)) or (reg_sum(8) xor reg_sum(7));

    msb_sum <= reg_sum(9);

    maxmin_mux: generic_mux2to1 port map (w0 => "01111111", w1 => "10000000", s => mux2to1_maxmin, f => maxmin);
    res_mux  :  generic_mux2to1 port map (w0 => std_logic_vector(reg_sum(7 downto 0)), w1 => maxmin, s => mux2to1_v_h, f => d_out);
    data_out <= signed( d_out ) ;
end behavior;