mee_moo_tester

------- mee_moo_tester ------
library ieee;
use ieee.std_logic_1164.all;

entity mee_moo_tester is
port(
    KEY, SW : in std_logic_vector(1 downto 0);
    LEDR    : out std_logic_vector(1 downto 0));
end mee_moo_tester;

architecture structural of mee_moo_tester is
begin

I1: entity work.mee_moo
     port map(
        clk     => KEY(0),
        reset   => KEY(1),
        inp     => SW,
        moo_out => LEDR(0),
        mee_out => LEDR(1));

end structural;