top module

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:31:47 05/19/2015
-- Design Name:
-- Module Name:    top_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_module is

    port(
        sysclk :in std_logic;

        --uart_tx: out std_logic;
        btn : in  STD_LOGIC_VECTOR (3 downto 0);
        --miso : in STD_LOGIC;
        tx : out std_logic;

        led1 : out std_logic;
        led2 : out std_logic

        );

end top_module;

architecture Behavioral of top_module is

signal tempX : std_logic_vector (11 downto 0);
signal tempY : std_logic_vector (11 downto 0);
signal tempZ : std_logic_vector (11 downto 0);
signal ZZ : std_logic_vector (7 downto 0);
signal YY : std_logic_vector (7 downto 0);
signal XX : std_logic_vector (7 downto 0);

signal clr: std_logic;



component ADXL362Ctrl
port
(
   SYSCLK     : in STD_LOGIC; -- System Clock
   RESET      : in STD_LOGIC;

   -- Accelerometer data signals
   ACCEL_X    : out STD_LOGIC_VECTOR (11 downto 0);
   ACCEL_Y    : out STD_LOGIC_VECTOR (11 downto 0);
   ACCEL_Z    : out STD_LOGIC_VECTOR (11 downto 0);

   --SPI Interface Signals
   SCLK       : out STD_LOGIC;
    MOSI       : out STD_LOGIC;
    MISO       : in STD_LOGIC;
    SS         : out STD_LOGIC

);
end component;



-- UART module
component t_serial is
port(
  sys_clk : in std_logic; -- 50 MHz system clock

  uart_tx : out std_logic;
  led1 : out std_logic;
  led2 : out std_logic;

  -- in data from acc
   Ax : in std_logic_vector (7 downto 0);
    Ay : in std_logic_vector (7 downto 0);
    Az : in std_logic_vector (7 downto 0);


  reset : in std_logic
);
end component;

-- convert data from 12 to 8 bit
component convertion is
port (
   ACCEL_X    : in STD_LOGIC_VECTOR (11 downto 0);
   ACCEL_Y    : in STD_LOGIC_VECTOR (11 downto 0);
   ACCEL_Z    : in STD_LOGIC_VECTOR (11 downto 0);

    Ax : out std_logic_vector (7 downto 0);
    Ay : out std_logic_vector (7 downto 0);
    Az : out std_logic_vector (7 downto 0)
    );
end component;

begin
    A : ADXL362Ctrl
--clr <= btn(3);
        port map
        (
            MISO => miso,
            SYSCLK => sysclk,
            RESET => btn(3),

            ACCEL_X => tempX,
            ACCEL_Y => tempY,
            ACCEL_Z => tempZ,
            --SPI Interface Signals
            SCLK        => sclk,
            MOSI        => mosi,
            MISO        => miso,
            SS          => ss
        );





    A3: convertion
        port map
            (
            Ay => YY,
            Az => ZZ,
            Ax => XX,
            ACCEL_X => tempX,
            ACCEL_Y => tempY,
            ACCEL_Z => tempZ
            );
--
    A4: t_serial
        port map
            (
            reset => btn(3),
            sys_clk => sysclk,
            Ax => XX,
            Ay => YY,
            Az => ZZ,
            uart_tx => tx,

            led1=>led1,
            led2=>led2
            );

end Behavioral;