Jk

library ieee;
use ieee.std_logic_1164.all;

entity JK is
port(J,K,clk:in std_logic;
        Q,Q2:buffer std_logic);
end JK;

architecture JackKilby of JK is
begin
process(clk,J,K)
        begin
            if (clk'event and clk='1') then
                if J='1' and K='0' then Q<= '1';Q2 <= '1';
                elsif K='1' and J='0' then Q<= '0';Q2 <='0';
                elsif K='1' and J='1' then Q <= not Q;Q2 <= not Q2;
                elsif K='0' and J='0' then Q <= Q; Q2<=Q2;
                end if;
            end if;
end process;
end JackKilby;