test_hmsclock

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_clock IS
END test_clock;

ARCHITECTURE behavior OF test_clock IS

    COMPONENT hmsclock
    PORT(
         Clk : IN  std_logic;
         En : IN  std_logic;
         Rst : IN  std_logic;
         Cout : OUT  std_logic;
         Hours : OUT  std_logic_vector(4 downto 0);
         Minutes : OUT  std_logic_vector(5 downto 0);
         Seconds : OUT  std_logic_vector(5 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal Clk : std_logic := '0';
   signal En : std_logic := '1';
   signal Rst : std_logic := '0';

    --Outputs
   signal Cout : std_logic := '0';
   signal H : std_logic_vector(4 downto 0) := "00000";
   signal M : std_logic_vector(5 downto 0) := "000000";
   signal S : std_logic_vector(5 downto 0) := "000000";

   -- Clock period definitions
   constant Clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: hmsclock PORT MAP (
          Clk => Clk,
          En => En,
          Rst => Rst,
          Cout => Cout,
          Hours => H,
          Minutes => M,
          Seconds => S
        );

   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

      wait for Clk_period*10000;

      -- insert stimulus here

      wait;
   end process;

END;