tb

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sekvkola_tb is
end sekvkola_tb;

architecture Test_tb of sekvkola_tb is
    signal sCLK : std_logic;
    signal sRST : std_logic;
    signal sGO : std_logic;
    signal sSTOP : std_logic;
    signal sMUXROW : std_logic_vector(1 downto 0);
    signal s7SEGM : std_logic_vector (6 downto 0);

    component sekvkola
        port(
            iCLK : in std_logic;
            iRST : in std_logic;
            iGO : in std_logic;
            iSTOP : in std_logic;
            oMUXROW : out std_logic_vector(1 downto 0);
            o7SEGM : out std_logic_vector (6 downto 0)
        );
    end component;

    constant iCLK_period : time := 83 ns;
begin
    uut : sekvkola port map (
        iCLK => sCLK,
        iRST => sRST,
        iGO => sGO,
        iSTOP => sSTOP,
        oMUXROW => sMUXROW,
        o7SEGM => s7SEGM
    );

    iCLK_process : process
    begin
        sCLK <= '0';
        wait for iCLK_period / 2;
        sCLK <= '1';
        wait for iCLK_period / 2;
    end process;

    stimulus : process
    begin
        sGO <= '0';
        sSTOP <= '0';

        sRST <= '1';
        wait for 3.33 * iCLK_period;
        sRST <= '0';

        sGO <= '1';
        wait for 3 * iCLK_period;

        sGO <= '0';
        wait for 3 * iCLK_period;

        sSTOP <= '1';
        wait for 2 * iCLK_period;

        sSTOP <= '0';
        sGO <= '1';

        wait;

    end process stimulus;

end architecture;