Test_bench for decoder 8 to 3

--18.01.2019 Igor Kojic

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec4to8_tb is
end dec4to8_tb;

architecture Behavioral of dec4to8_tb is
component dec4to8
port(
    y: in std_logic_vector(2 downto 0);
    x: out std_logic_vector(7 downto 0)
);
end component;

signal y: std_logic_vector(2 downto 0);
signal x: std_logic_vector(7 downto 0);

begin utt:
dec4to8 port map(
    y => y,
    x => x
);

    y <= "101" after 2 us;


end Behavioral;