Guest User

Untitled

a guest
Feb 19th, 2018
63
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VHDL 0.24 KB | None | 0 0
  1. entity Etunimi_Sukunimi_VT2_P1_integer_DIV is port(
  2.     A,B: in integer range -16 to 15;
  3.     Y: out integer range -32 to 30);
  4. end entity;
  5. architecture Integer_DIV of Etunimi_Sukunimi_VT2_P1_integer_DIV is
  6. begin
  7. Y <= A / B;
  8. end architecture;
Add Comment
Please, Sign In to add comment