library IEEE;
use IEEE.STD_LOGIC_1164.all;
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entity vand4 is
    port (i1 : in  std_logic;
            i2 : in  std_logic;
            i3 : in  std_logic;
            i4 : in  std_logic;
            o : out  std_logic);
end vand4;
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architecture df1 of vand4 is
begin
    o <= i1 and i2 and i3 and i4 after 1 ns;
end df1;
--------------------------------------------------