top

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
  port(
    clk, rst, start : in std_logic;
    i : in std_logic_vector(4 downto 0);
    an : out std_logic_vector(3 downto 0);
    sseg : out std_logic_vector (7 downto 0)
  );
end entity;

architecture arch of top is

  component fibonacci is
    port(clk, rst : in std_logic;                                          --entrada padrão lógico
    start : in std_logic;                                             --entrada padrão lógico
    i : in std_logic_vector(4 downto 0);
    ready, done : out std_logic;                                      --saída padrão lógico
    f : out std_logic_vector(12 downto 0)
    );
  end component;

  component binttobcd is
    port(
      clk : in std_logic;
    rst : in std_logic;
    start : in std_logic;
    bin : in std_logic_vector ( 12 downto 0 );
    ready, done : out std_logic;
    bcd3,bcd2,bcd1,bcd0 : out std_logic_vector (3 downto 0)
    );
  end component;

  component display7 is
    port(clk, rst : in std_logic;
  an : out std_logic_vector(3 downto 0);
  sseg : out std_logic_vector (7 downto 0);
  in3, in2, in1, in0 : in std_logic_vector(3 downto 0)
    );
  end component;

  signal ready : std_logic;
  signal resetInv : std_logic;
  signal startInv : std_logic;
  signal doneFib : std_logic;
  signal doneBinToBcd : std_logic;
  signal bcd00 : std_logic_vector(3 downto 0);
  signal bcd01 : std_logic_vector(3 downto 0);
  signal bcd02 : std_logic_vector(3 downto 0);
  signal bcd03 : std_logic_vector(3 downto 0);
  signal fibon : std_logic_vector(12 downto 0);

  begin

  resetInv <= not reset;
  startInv <= not start;

 fibonacci     port map(clock,  resetInv,   startInv,   i,  open,   doneFib,    fibon);
 binttobcd      port map(clock, resetInv,   doneFib,    fibon,  open,   doneBinToBcd,   bcd03,  bcd02,  bcd01,  bcd00);
display7 port map(clock,    resetInv,   bcd03,  bcd02,  bcd01,  bcd00,  an, sseg);

end arch;