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DomMisterSoja Apr 12th, 2018 84 Never
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity top is
  6.   port(
  7.     clk, rst, start : in std_logic;
  8.     i : in std_logic_vector(4 downto 0);
  9.     an : out std_logic_vector(3 downto 0);
  10.     sseg : out std_logic_vector (7 downto 0)
  11.   );
  12. end entity;
  13.  
  14. architecture arch of top is
  15.  
  16.   component fibonacci is
  17.     port(clk, rst : in std_logic;                                          --entrada padrão lógico
  18.     start : in std_logic;                                             --entrada padrão lógico
  19.     i : in std_logic_vector(4 downto 0);
  20.     ready, done : out std_logic;                                      --saída padrão lógico
  21.     f : out std_logic_vector(12 downto 0)
  22.     );
  23.   end component;
  24.  
  25.   component binttobcd is
  26.     port(
  27.       clk : in std_logic;
  28.     rst : in std_logic;
  29.     start : in std_logic;
  30.     bin : in std_logic_vector ( 12 downto 0 );
  31.     ready, done : out std_logic;
  32.     bcd3,bcd2,bcd1,bcd0 : out std_logic_vector (3 downto 0)
  33.     );
  34.   end component;
  35.  
  36.   component display7 is
  37.     port(clk, rst : in std_logic;
  38.   an : out std_logic_vector(3 downto 0);
  39.   sseg : out std_logic_vector (7 downto 0);
  40.   in3, in2, in1, in0 : in std_logic_vector(3 downto 0)
  41.     );
  42.   end component;
  43.  
  44.   signal ready : std_logic;
  45.   signal resetInv : std_logic;
  46.   signal startInv : std_logic;  
  47.   signal doneFib : std_logic;
  48.   signal doneBinToBcd : std_logic;
  49.   signal bcd00 : std_logic_vector(3 downto 0);
  50.   signal bcd01 : std_logic_vector(3 downto 0);
  51.   signal bcd02 : std_logic_vector(3 downto 0);
  52.   signal bcd03 : std_logic_vector(3 downto 0);
  53.   signal fibon : std_logic_vector(12 downto 0);
  54.  
  55.   begin
  56.  
  57.   resetInv <= not reset;
  58.   startInv <= not start;  
  59.  
  60.  fibonacci     port map(clock,  resetInv,   startInv,   i,  open,   doneFib,    fibon);
  61.  binttobcd      port map(clock, resetInv,   doneFib,    fibon,  open,   doneBinToBcd,   bcd03,  bcd02,  bcd01,  bcd00);
  62. display7 port map(clock,    resetInv,   bcd03,  bcd02,  bcd01,  bcd00,  an, sseg);
  63.  
  64. end arch;
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