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-- Company:
-- Engineer:
--
-- Create Date:    12:51:57 07/14/2012
-- Design Name:
-- Module Name:    Contador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Contador is
    Port ( ClkSig : in  STD_LOGIC;
           Sel : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           Output : out  STD_LOGIC_VECTOR (3 downto 0));
end Contador;

architecture Behavioral of Contador is
signal Count: Integer range 0 to 9;

begin

select_process: process
begin
if ClkSig'event and ClkSig = '1' then
    if Reset ='1' then
        if sel = '0' then
                Count<= 9;
        elsif sel ='1' then
                Count<= 0;
        end  if;
    elsif Reset ='0' then
        if sel = '0' then
                Count<= Count -1;
        elsif sel ='1' then
                Count<= Count +1;
        end  if;
    end if;
end if;

case Count is
    when '0' => output<= "0000";
    when '1' => output<= "0001";
    when '2' => output<= "0010";
    when '3' => output<= "0011";
    when '4' => output<= "0100";
    when '5' => output<= "0101";
    when '6' => output<= "0110";
    when '7' => output<= "0111";
    when '8' => output<= "1000";
    when '9' => output<= "1001";

end case;
end process;
end Behavioral;