LIBRARY  ieee;
USE ieee.std_logic_1164.all;

entity vga_driver is
    port(
        in_clk_50 : in std_logic;      -- vga clock
        out_xSync : out std_logic;  -- horizontal sync
        out_ySync : out std_logic;  -- vertical sync
        out_R :  out std_logic_vector(9 downto 0);
        out_G :  out std_logic_vector(9 downto 0);
        out_B :  out std_logic_vector(9 downto 0);
        out_blank : out std_logic;
        out_sync : out std_logic;
        out_clk : out std_logic
        );
end vga_driver;

architecture driver of vga_driver is
    signal half_clock: std_logic;
    signal x_full: integer range 0 to 800 := 0;
    signal y_full: integer range 0 to 525 := 0;
    signal xSyncEnable: std_logic;
    signal ySyncEnable: std_logic;
    signal x: integer range 0 to 639 := 0;
    signal video_on: std_logic;
    signal y: integer range 0 to 479 := 0;

    --horizontal constants
    constant x_visible_area : natural := 640; -- horizontal visible area
    constant x_front_porch : natural := 16;  -- horizontal front porch
    constant x_sync_pulse : natural := 96;  -- horizontal sync pulse
    constant x_back_porch : natural := 48;  -- horizontal back porch
    constant x_total : natural := 800;

    --vertical constants
    constant y_visible_area : natural := 480;
    constant y_front_porch : natural := 10;
    constant y_back_porch : natural := 33;
    constant y_sync_pulse : natural := 2;
    constant y_total : natural := 525;

    begin
        out_sync <= '0';
        out_blank <= '1';
        out_xSync <= xSyncEnable;
        out_ySync <= ySyncEnable;
        out_clk <= half_clock;

        -- HALFING THE CLOCK --
        clockScale: process(in_clk_50)
        begin
            if in_clk_50'event and in_clk_50 = '1' then
                half_clock <= not half_clock;
            end if;
        end process clockScale;

        -- SIGNALS TIMING --
        sig_timing: process(half_clock)
        begin
            if half_clock'event and half_clock = '1' then
                if x_full = x_total then

                    x_full <= 0;
                    y_full <= y_full + 1;

                    if y_full = y_total then
                        y_full <= 0;
                    else
                        y_full <= y_full + 1;
                    end if;
                else
                    x_full <= x_full + 1;
                end if;
            end if;
        end process sig_timing;


        -- SYNC VGA SIGNAL --
        vga_sync: process (half_clock)
        begin

            if half_clock'event and half_clock = '1' then
                if x_full >= (x_visible_area + x_front_porch) and x_full < (x_visible_area + x_front_porch + x_sync_pulse)  then --96 points
                    xSyncEnable <= '0';
                else
                    xSyncEnable <= '1';
                end if;

                if y_full >= (y_visible_area + y_front_porch) and y_full < (y_visible_area + y_front_porch + y_sync_pulse) then --2 points
                    ySyncEnable <= '0';
                else
                    ySyncEnable <= '1';
                end if;
            end if;
        end process vga_sync;



        foreground: process(half_clock)
            begin
                if half_clock'event and half_clock = '1' then
                    if( x_full > 120 and x_full < 240 and y_full > 150 and y_full < 250) then
                        out_R(9) <= '0';
                        out_G(9) <= '1';
                        out_B(9) <= '1';

                    else
                        out_R(9) <= '0';
                        out_G(9) <= '0';
                        out_B(9) <= '0';
                    end if;
                end if;
            end process foreground;

end driver;