library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clocks_reset_gen is
    port (
        clock : in std_logic;
        clock50 : out std_logic;
        clock200 : out std_logic;
        reset : out std_logic
    );
end entity clocks_reset_gen;

architecture Behavioral of clocks_reset_gen is
    signal clkin_ibufg : std_logic;
    signal dcm_reset : std_logic;
    signal locked : std_logic;
--  signal reset_in2 : std_logic := '1';
    signal reset_in2 : std_logic;
    signal clock50_sig : std_logic;
begin

    clock50 <= clock50_sig;

    Inst_reset1: entity work.reset
    PORT MAP(
        clock => clkin_ibufg,
        reset_in => '0',
        reset => dcm_reset
    );

    reset_in2 <= not locked;
    Inst_reset2: entity work.reset
    PORT MAP(
        clock => clock50_sig,
        reset_in => reset_in2,
        reset => reset
    );

    Inst_DCM_BRAM: entity work.DCM_BRAM
    GENERIC MAP(
        CLKFX_MULTIPLY => 5
    )
    PORT MAP(
        CLKIN_IN => clock,
        RST_IN => dcm_reset,
        CLKFX_OUT => clock200,
        CLKIN_IBUFG_OUT => clkin_ibufg,
        CLK0_OUT => clock50_sig,
        LOCKED_OUT => locked
    );

end;