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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include <drm/drmP.h>
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. #include "atom.h"
  32.  
  33. #include <linux/firmware.h>
  34. #include <linux/slab.h>
  35. #include <linux/acpi.h>
  36. /*
  37.  * BIOS.
  38.  */
  39.  
  40. /* If you boot an IGP board with a discrete card as the primary,
  41.  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42.  * part of the system bios.  On boot, the system bios puts a
  43.  * copy of the igp rom at the start of vram if a discrete card is
  44.  * present.
  45.  */
  46. static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47. {
  48.     uint8_t __iomem *bios;
  49.     resource_size_t vram_base;
  50.     resource_size_t size = 256 * 1024; /* ??? */
  51.  
  52.     if (!(rdev->flags & RADEON_IS_IGP))
  53.         if (!radeon_card_posted(rdev))
  54.             return false;
  55.  
  56.     rdev->bios = NULL;
  57.     vram_base = pci_resource_start(rdev->pdev, 0);
  58.     bios = ioremap(vram_base, size);
  59.     if (!bios) {
  60.         DRM_ERROR("No bios\n");
  61.         return false;
  62.     }
  63.  
  64.     if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  65.         iounmap(bios);
  66.         return false;
  67.     }
  68.     rdev->bios = kmalloc(size, GFP_KERNEL);
  69.     if (rdev->bios == NULL) {
  70.         DRM_ERROR("alloc fail\n");
  71.         iounmap(bios);
  72.         return false;
  73.     }
  74.     memcpy_fromio(rdev->bios, bios, size);
  75.     iounmap(bios);
  76.     return true;
  77. }
  78.  
  79. static bool radeon_read_bios_from_firmware(struct radeon_device *rdev)
  80. {
  81.     const uint8_t __iomem *bios;
  82.     resource_size_t size;
  83.     const struct firmware *fw = NULL;
  84.  
  85.     request_firmware(&fw, "radeon/vbios.bin", rdev->dev);
  86.     if (!fw) {
  87.         DRM_ERROR("No bios\n");
  88.         return false;
  89.     }
  90.     size = fw->size;
  91.     bios = fw->data;
  92.  
  93.     if (!bios) {
  94.         DRM_ERROR("No bios\n");
  95.         return false;
  96.     }
  97.  
  98.     if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  99.         DRM_ERROR("wrong sig\n");
  100.         release_firmware(fw);
  101.         return false;
  102.     }
  103.     rdev->bios = kmalloc(size, GFP_KERNEL);
  104.     if (rdev->bios == NULL) {
  105.         DRM_ERROR("alloc fail\n");
  106.         release_firmware(fw);
  107.         return false;
  108.     }
  109.     memcpy(rdev->bios, bios, size);
  110.     release_firmware(fw);
  111.     return true;
  112. }
  113.  
  114. static bool radeon_read_bios(struct radeon_device *rdev)
  115. {
  116.     uint8_t __iomem *bios, val1, val2;
  117.     size_t size;
  118.  
  119.     rdev->bios = NULL;
  120.     /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  121.     bios = pci_map_rom(rdev->pdev, &size);
  122.     if (!bios) {
  123.         return false;
  124.     }
  125.  
  126.     val1 = readb(&bios[0]);
  127.     val2 = readb(&bios[1]);
  128.  
  129.     if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
  130.         pci_unmap_rom(rdev->pdev, bios);
  131.         return false;
  132.     }
  133.     rdev->bios = kzalloc(size, GFP_KERNEL);
  134.     if (rdev->bios == NULL) {
  135.         pci_unmap_rom(rdev->pdev, bios);
  136.         return false;
  137.     }
  138.     memcpy_fromio(rdev->bios, bios, size);
  139.     pci_unmap_rom(rdev->pdev, bios);
  140.     return true;
  141. }
  142.  
  143. static bool radeon_read_platform_bios(struct radeon_device *rdev)
  144. {
  145.     uint8_t __iomem *bios;
  146.     size_t size;
  147.  
  148.     rdev->bios = NULL;
  149.  
  150.     bios = pci_platform_rom(rdev->pdev, &size);
  151.     if (!bios) {
  152.         return false;
  153.     }
  154.  
  155.     if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  156.         return false;
  157.     }
  158.     rdev->bios = kmemdup(bios, size, GFP_KERNEL);
  159.     if (rdev->bios == NULL) {
  160.         return false;
  161.     }
  162.  
  163.     return true;
  164. }
  165.  
  166. #ifdef CONFIG_ACPI
  167. /* ATRM is used to get the BIOS on the discrete cards in
  168.  * dual-gpu systems.
  169.  */
  170. /* retrieve the ROM in 4k blocks */
  171. #define ATRM_BIOS_PAGE 4096
  172. /**
  173.  * radeon_atrm_call - fetch a chunk of the vbios
  174.  *
  175.  * @atrm_handle: acpi ATRM handle
  176.  * @bios: vbios image pointer
  177.  * @offset: offset of vbios image data to fetch
  178.  * @len: length of vbios image data to fetch
  179.  *
  180.  * Executes ATRM to fetch a chunk of the discrete
  181.  * vbios image on PX systems (all asics).
  182.  * Returns the length of the buffer fetched.
  183.  */
  184. static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
  185.                 int offset, int len)
  186. {
  187.     acpi_status status;
  188.     union acpi_object atrm_arg_elements[2], *obj;
  189.     struct acpi_object_list atrm_arg;
  190.     struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
  191.  
  192.     atrm_arg.count = 2;
  193.     atrm_arg.pointer = &atrm_arg_elements[0];
  194.  
  195.     atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
  196.     atrm_arg_elements[0].integer.value = offset;
  197.  
  198.     atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
  199.     atrm_arg_elements[1].integer.value = len;
  200.  
  201.     status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
  202.     if (ACPI_FAILURE(status)) {
  203.         printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
  204.         return -ENODEV;
  205.     }
  206.  
  207.     obj = (union acpi_object *)buffer.pointer;
  208.     memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
  209.     len = obj->buffer.length;
  210.     kfree(buffer.pointer);
  211.     return len;
  212. }
  213.  
  214. static bool radeon_atrm_get_bios(struct radeon_device *rdev)
  215. {
  216.     int ret;
  217.     int size = 256 * 1024;
  218.     int i;
  219.     struct pci_dev *pdev = NULL;
  220.     acpi_handle dhandle, atrm_handle;
  221.     acpi_status status;
  222.     bool found = false;
  223.  
  224.     /* ATRM is for the discrete card only */
  225.     if (rdev->flags & RADEON_IS_IGP)
  226.         return false;
  227.  
  228.     while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
  229.         dhandle = ACPI_HANDLE(&pdev->dev);
  230.         if (!dhandle)
  231.             continue;
  232.  
  233.         status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
  234.         if (!ACPI_FAILURE(status)) {
  235.             found = true;
  236.             break;
  237.         }
  238.     }
  239.  
  240.     if (!found) {
  241.         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
  242.             dhandle = ACPI_HANDLE(&pdev->dev);
  243.             if (!dhandle)
  244.                 continue;
  245.  
  246.             status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
  247.             if (!ACPI_FAILURE(status)) {
  248.                 found = true;
  249.                 break;
  250.             }
  251.         }
  252.     }
  253.  
  254.     if (!found)
  255.         return false;
  256.  
  257.     rdev->bios = kmalloc(size, GFP_KERNEL);
  258.     if (!rdev->bios) {
  259.         DRM_ERROR("Unable to allocate bios\n");
  260.         return false;
  261.     }
  262.  
  263.     for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
  264.         ret = radeon_atrm_call(atrm_handle,
  265.                        rdev->bios,
  266.                        (i * ATRM_BIOS_PAGE),
  267.                        ATRM_BIOS_PAGE);
  268.         if (ret < ATRM_BIOS_PAGE)
  269.             break;
  270.     }
  271.  
  272.     if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  273.         kfree(rdev->bios);
  274.         return false;
  275.     }
  276.     return true;
  277. }
  278. #else
  279. static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
  280. {
  281.     return false;
  282. }
  283. #endif
  284.  
  285. static bool ni_read_disabled_bios(struct radeon_device *rdev)
  286. {
  287.     u32 bus_cntl;
  288.     u32 d1vga_control;
  289.     u32 d2vga_control;
  290.     u32 vga_render_control;
  291.     u32 rom_cntl;
  292.     bool r;
  293.  
  294.     bus_cntl = RREG32(R600_BUS_CNTL);
  295.     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  296.     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  297.     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  298.     rom_cntl = RREG32(R600_ROM_CNTL);
  299.  
  300.     /* enable the rom */
  301.     WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
  302.     if (!ASIC_IS_NODCE(rdev)) {
  303.         /* Disable VGA mode */
  304.         WREG32(AVIVO_D1VGA_CONTROL,
  305.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  306.                       AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  307.         WREG32(AVIVO_D2VGA_CONTROL,
  308.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  309.                       AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  310.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  311.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  312.     }
  313.     WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
  314.  
  315.     r = radeon_read_bios(rdev);
  316.  
  317.     /* restore regs */
  318.     WREG32(R600_BUS_CNTL, bus_cntl);
  319.     if (!ASIC_IS_NODCE(rdev)) {
  320.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  321.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  322.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  323.     }
  324.     WREG32(R600_ROM_CNTL, rom_cntl);
  325.     return r;
  326. }
  327.  
  328. static bool r700_read_disabled_bios(struct radeon_device *rdev)
  329. {
  330.     uint32_t viph_control;
  331.     uint32_t bus_cntl;
  332.     uint32_t d1vga_control;
  333.     uint32_t d2vga_control;
  334.     uint32_t vga_render_control;
  335.     uint32_t rom_cntl;
  336.     uint32_t cg_spll_func_cntl = 0;
  337.     uint32_t cg_spll_status;
  338.     bool r;
  339.  
  340.     viph_control = RREG32(RADEON_VIPH_CONTROL);
  341.     bus_cntl = RREG32(R600_BUS_CNTL);
  342.     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  343.     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  344.     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  345.     rom_cntl = RREG32(R600_ROM_CNTL);
  346.  
  347.     /* disable VIP */
  348.     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  349.     /* enable the rom */
  350.     WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
  351.     /* Disable VGA mode */
  352.     WREG32(AVIVO_D1VGA_CONTROL,
  353.            (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  354.         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  355.     WREG32(AVIVO_D2VGA_CONTROL,
  356.            (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  357.         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  358.     WREG32(AVIVO_VGA_RENDER_CONTROL,
  359.            (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  360.  
  361.     if (rdev->family == CHIP_RV730) {
  362.         cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
  363.  
  364.         /* enable bypass mode */
  365.         WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
  366.                         R600_SPLL_BYPASS_EN));
  367.  
  368.         /* wait for SPLL_CHG_STATUS to change to 1 */
  369.         cg_spll_status = 0;
  370.         while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  371.             cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  372.  
  373.         WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
  374.     } else
  375.         WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
  376.  
  377.     r = radeon_read_bios(rdev);
  378.  
  379.     /* restore regs */
  380.     if (rdev->family == CHIP_RV730) {
  381.         WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
  382.  
  383.         /* wait for SPLL_CHG_STATUS to change to 1 */
  384.         cg_spll_status = 0;
  385.         while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  386.             cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  387.     }
  388.     WREG32(RADEON_VIPH_CONTROL, viph_control);
  389.     WREG32(R600_BUS_CNTL, bus_cntl);
  390.     WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  391.     WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  392.     WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  393.     WREG32(R600_ROM_CNTL, rom_cntl);
  394.     return r;
  395. }
  396.  
  397. static bool r600_read_disabled_bios(struct radeon_device *rdev)
  398. {
  399.     uint32_t viph_control;
  400.     uint32_t bus_cntl;
  401.     uint32_t d1vga_control;
  402.     uint32_t d2vga_control;
  403.     uint32_t vga_render_control;
  404.     uint32_t rom_cntl;
  405.     uint32_t general_pwrmgt;
  406.     uint32_t low_vid_lower_gpio_cntl;
  407.     uint32_t medium_vid_lower_gpio_cntl;
  408.     uint32_t high_vid_lower_gpio_cntl;
  409.     uint32_t ctxsw_vid_lower_gpio_cntl;
  410.     uint32_t lower_gpio_enable;
  411.     bool r;
  412.  
  413.     viph_control = RREG32(RADEON_VIPH_CONTROL);
  414.     bus_cntl = RREG32(R600_BUS_CNTL);
  415.     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  416.     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  417.     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  418.     rom_cntl = RREG32(R600_ROM_CNTL);
  419.     general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
  420.     low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
  421.     medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
  422.     high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
  423.     ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
  424.     lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
  425.  
  426.     /* disable VIP */
  427.     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  428.     /* enable the rom */
  429.     WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
  430.     /* Disable VGA mode */
  431.     WREG32(AVIVO_D1VGA_CONTROL,
  432.            (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  433.         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  434.     WREG32(AVIVO_D2VGA_CONTROL,
  435.            (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  436.         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  437.     WREG32(AVIVO_VGA_RENDER_CONTROL,
  438.            (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  439.  
  440.     WREG32(R600_ROM_CNTL,
  441.            ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
  442.         (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
  443.         R600_SCK_OVERWRITE));
  444.  
  445.     WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
  446.     WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
  447.            (low_vid_lower_gpio_cntl & ~0x400));
  448.     WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
  449.            (medium_vid_lower_gpio_cntl & ~0x400));
  450.     WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
  451.            (high_vid_lower_gpio_cntl & ~0x400));
  452.     WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
  453.            (ctxsw_vid_lower_gpio_cntl & ~0x400));
  454.     WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
  455.  
  456.     r = radeon_read_bios(rdev);
  457.  
  458.     /* restore regs */
  459.     WREG32(RADEON_VIPH_CONTROL, viph_control);
  460.     WREG32(R600_BUS_CNTL, bus_cntl);
  461.     WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  462.     WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  463.     WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  464.     WREG32(R600_ROM_CNTL, rom_cntl);
  465.     WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
  466.     WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
  467.     WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
  468.     WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
  469.     WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
  470.     WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
  471.     return r;
  472. }
  473.  
  474. static bool avivo_read_disabled_bios(struct radeon_device *rdev)
  475. {
  476.     uint32_t seprom_cntl1;
  477.     uint32_t viph_control;
  478.     uint32_t bus_cntl;
  479.     uint32_t d1vga_control;
  480.     uint32_t d2vga_control;
  481.     uint32_t vga_render_control;
  482.     uint32_t gpiopad_a;
  483.     uint32_t gpiopad_en;
  484.     uint32_t gpiopad_mask;
  485.     bool r;
  486.  
  487.     seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  488.     viph_control = RREG32(RADEON_VIPH_CONTROL);
  489.     bus_cntl = RREG32(RV370_BUS_CNTL);
  490.     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  491.     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  492.     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  493.     gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  494.     gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
  495.     gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
  496.  
  497.     WREG32(RADEON_SEPROM_CNTL1,
  498.            ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  499.         (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  500.     WREG32(RADEON_GPIOPAD_A, 0);
  501.     WREG32(RADEON_GPIOPAD_EN, 0);
  502.     WREG32(RADEON_GPIOPAD_MASK, 0);
  503.  
  504.     /* disable VIP */
  505.     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  506.  
  507.     /* enable the rom */
  508.     WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
  509.  
  510.     /* Disable VGA mode */
  511.     WREG32(AVIVO_D1VGA_CONTROL,
  512.            (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  513.         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  514.     WREG32(AVIVO_D2VGA_CONTROL,
  515.            (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  516.         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  517.     WREG32(AVIVO_VGA_RENDER_CONTROL,
  518.            (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  519.  
  520.     r = radeon_read_bios(rdev);
  521.  
  522.     /* restore regs */
  523.     WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  524.     WREG32(RADEON_VIPH_CONTROL, viph_control);
  525.     WREG32(RV370_BUS_CNTL, bus_cntl);
  526.     WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  527.     WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  528.     WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  529.     WREG32(RADEON_GPIOPAD_A, gpiopad_a);
  530.     WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
  531.     WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
  532.     return r;
  533. }
  534.  
  535. static bool legacy_read_disabled_bios(struct radeon_device *rdev)
  536. {
  537.     uint32_t seprom_cntl1;
  538.     uint32_t viph_control;
  539.     uint32_t bus_cntl;
  540.     uint32_t crtc_gen_cntl;
  541.     uint32_t crtc2_gen_cntl;
  542.     uint32_t crtc_ext_cntl;
  543.     uint32_t fp2_gen_cntl;
  544.     bool r;
  545.  
  546.     seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  547.     viph_control = RREG32(RADEON_VIPH_CONTROL);
  548.     if (rdev->flags & RADEON_IS_PCIE)
  549.         bus_cntl = RREG32(RV370_BUS_CNTL);
  550.     else
  551.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  552.     crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  553.     crtc2_gen_cntl = 0;
  554.     crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  555.     fp2_gen_cntl = 0;
  556.  
  557.     if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  558.         fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  559.     }
  560.  
  561.     if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  562.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  563.     }
  564.  
  565.     WREG32(RADEON_SEPROM_CNTL1,
  566.            ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  567.         (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  568.  
  569.     /* disable VIP */
  570.     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  571.  
  572.     /* enable the rom */
  573.     if (rdev->flags & RADEON_IS_PCIE)
  574.         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
  575.     else
  576.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  577.  
  578.     /* Turn off mem requests and CRTC for both controllers */
  579.     WREG32(RADEON_CRTC_GEN_CNTL,
  580.            ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
  581.         (RADEON_CRTC_DISP_REQ_EN_B |
  582.          RADEON_CRTC_EXT_DISP_EN)));
  583.     if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  584.         WREG32(RADEON_CRTC2_GEN_CNTL,
  585.                ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
  586.             RADEON_CRTC2_DISP_REQ_EN_B));
  587.     }
  588.     /* Turn off CRTC */
  589.     WREG32(RADEON_CRTC_EXT_CNTL,
  590.            ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
  591.         (RADEON_CRTC_SYNC_TRISTAT |
  592.          RADEON_CRTC_DISPLAY_DIS)));
  593.  
  594.     if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  595.         WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
  596.     }
  597.  
  598.     r = radeon_read_bios(rdev);
  599.  
  600.     /* restore regs */
  601.     WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  602.     WREG32(RADEON_VIPH_CONTROL, viph_control);
  603.     if (rdev->flags & RADEON_IS_PCIE)
  604.         WREG32(RV370_BUS_CNTL, bus_cntl);
  605.     else
  606.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  607.     WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
  608.     if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  609.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  610.     }
  611.     WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  612.     if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  613.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  614.     }
  615.     return r;
  616. }
  617.  
  618. static bool radeon_read_disabled_bios(struct radeon_device *rdev)
  619. {
  620.     if (rdev->flags & RADEON_IS_IGP)
  621.         return igp_read_bios_from_vram(rdev);
  622.     else if (rdev->family >= CHIP_BARTS)
  623.         return ni_read_disabled_bios(rdev);
  624.     else if (rdev->family >= CHIP_RV770)
  625.         return r700_read_disabled_bios(rdev);
  626.     else if (rdev->family >= CHIP_R600)
  627.         return r600_read_disabled_bios(rdev);
  628.     else if (rdev->family >= CHIP_RS600)
  629.         return avivo_read_disabled_bios(rdev);
  630.     else
  631.         return legacy_read_disabled_bios(rdev);
  632. }
  633.  
  634. #ifdef CONFIG_ACPI
  635. static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
  636. {
  637.     struct acpi_table_header *hdr;
  638.     acpi_size tbl_size;
  639.     UEFI_ACPI_VFCT *vfct;
  640.     unsigned offset;
  641.  
  642.     if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
  643.         return false;
  644.     tbl_size = hdr->length;
  645.     if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
  646.         DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
  647.         return false;
  648.     }
  649.  
  650.     vfct = (UEFI_ACPI_VFCT *)hdr;
  651.     offset = vfct->VBIOSImageOffset;
  652.  
  653.     while (offset < tbl_size) {
  654.         GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
  655.         VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
  656.  
  657.         offset += sizeof(VFCT_IMAGE_HEADER);
  658.         if (offset > tbl_size) {
  659.             DRM_ERROR("ACPI VFCT image header truncated\n");
  660.             return false;
  661.         }
  662.  
  663.         offset += vhdr->ImageLength;
  664.         if (offset > tbl_size) {
  665.             DRM_ERROR("ACPI VFCT image truncated\n");
  666.             return false;
  667.         }
  668.  
  669.         if (vhdr->ImageLength &&
  670.             vhdr->PCIBus == rdev->pdev->bus->number &&
  671.             vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
  672.             vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
  673.             vhdr->VendorID == rdev->pdev->vendor &&
  674.             vhdr->DeviceID == rdev->pdev->device) {
  675.             rdev->bios = kmemdup(&vbios->VbiosContent,
  676.                          vhdr->ImageLength,
  677.                          GFP_KERNEL);
  678.  
  679.             if (!rdev->bios)
  680.                 return false;
  681.             return true;
  682.         }
  683.     }
  684.  
  685.     DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
  686.     return false;
  687. }
  688. #else
  689. static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
  690. {
  691.     return false;
  692. }
  693. #endif
  694.  
  695. bool radeon_get_bios(struct radeon_device *rdev)
  696. {
  697.     bool r;
  698.     uint16_t tmp;
  699.  
  700.     r = radeon_atrm_get_bios(rdev);
  701.     if (r == false)
  702.         r = radeon_acpi_vfct_bios(rdev);
  703.     if (r == false)
  704.         r = igp_read_bios_from_vram(rdev);
  705.     if (r == false)
  706.         r = radeon_read_bios(rdev);
  707.     if (r == false) {
  708.         r = radeon_read_disabled_bios(rdev);
  709.         if (r == false) {
  710.             r = radeon_read_bios_from_firmware(rdev);
  711.         }
  712.     }
  713.     if (r == false)
  714.         r = radeon_read_platform_bios(rdev);
  715.     if (r == false || rdev->bios == NULL) {
  716.         DRM_ERROR("Unable to locate a BIOS ROM\n");
  717.         rdev->bios = NULL;
  718.         return false;
  719.     }
  720.     if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  721.         printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
  722.         goto free_bios;
  723.     }
  724.  
  725.     tmp = RBIOS16(0x18);
  726.     if (RBIOS8(tmp + 0x14) != 0x0) {
  727.         DRM_INFO("Not an x86 BIOS ROM, not using.\n");
  728.         goto free_bios;
  729.     }
  730.  
  731.     rdev->bios_header_start = RBIOS16(0x48);
  732.     if (!rdev->bios_header_start) {
  733.         goto free_bios;
  734.     }
  735.     tmp = rdev->bios_header_start + 4;
  736.     if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
  737.         !memcmp(rdev->bios + tmp, "MOTA", 4)) {
  738.         rdev->is_atom_bios = true;
  739.     } else {
  740.         rdev->is_atom_bios = false;
  741.     }
  742.  
  743.     DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
  744.     return true;
  745. free_bios:
  746.     kfree(rdev->bios);
  747.     rdev->bios = NULL;
  748.     return false;
  749. }
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