Coffee Fsm Testbench

library ieee;
use ieee.std_logic_1164.all;

entity F_tb is
end F_tb;

architecture arch of F_tb is

    component F is
    port(
        clk, input, areset: in std_logic;
        output: out std_logic_vector(2 downto 0)
    );
    end component;

    signal input, areset, clk: std_logic:='0';

    signal output: std_logic_vector(2 downto 0);

    constant clk_period: time:= 100ps;

    begin

    F_circuit: F port map(clk, input, areset, output);

    process
    begin
        clk<='0';
        wait for clk_period/2;
        clk<='1';
        wait for clk_period/2;
    end process;

    process
        begin
        areset <= '1';
        input <= '1';
        wait for clk_period*3/4;
        areset <= '0';
        wait for clk_period*21/4;
        input <= '0';
        wait for clk_period*2;
        input <= '1';
        wait;
    end process;

end arch;