watch_tester

--------- watch_tester -----------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity watch_tester is
port(
    KEY         : in std_logic_vector(3 downto 0);
    CLOCK_50    : in std_logic;
    HEX0        : out std_logic_vector(6 downto 0);
    HEX1        : out std_logic_vector(6 downto 0);
    HEX2        : out std_logic_vector(6 downto 0);
    HEX3        : out std_logic_vector(6 downto 0);
    HEX4        : out std_logic_vector(6 downto 0);
    HEX5        : out std_logic_vector(6 downto 0);
    HEX6        : out std_logic_vector(6 downto 0);
    HEX7        : out std_logic_vector(6 downto 0));

end watch_tester;

architecture structural of watch_tester is
begin

H10Bin: entity work.watch
     port map(
            clk     => CLOCK_50,
            speed   => KEY(0),
            reset   => KEY(3),
            sec_1   => HEX2,
            sec_10  => HEX3,
            min_1   => HEX4,
            min_10  => HEX5,
            hrs_1   => HEX6,
            hrs_10  => HEX7);

            HEX0    <= "1111111";
            HEX1    <= "1111111";

end structural;