STM32F4xx MCO1/MCO2 code

void rcc_mco1_enable()
{
    rcc_periph_clock_enable(RCC_GPIOA);
    gpio_mode_setup(
            GPIOA,
            GPIO_MODE_AF,
            GPIO_PUPD_NONE,
            GPIO8
            );
    gpio_set_af(
            GPIOA,
            GPIO_AF0,
            GPIO8
            );
    gpio_set_output_options(
            GPIOA,
            GPIO_OTYPE_PP,
            GPIO_OSPEED_100MHZ,
            GPIO8
            );
}

void rcc_mco2_enable()
{
    rcc_periph_clock_enable(RCC_GPIOC);
    gpio_mode_setup(
            GPIOC,
            GPIO_MODE_AF,
            GPIO_PUPD_NONE,
            GPIO9
            );
    gpio_set_af(
            GPIOC,
            GPIO_AF0,
            GPIO9
            );
    gpio_set_output_options(
            GPIOC,
            GPIO_OTYPE_PP,
            GPIO_OSPEED_100MHZ,
            GPIO9
            );
}

void rcc_mco1_set_source(uint8_t src)
{
    // Clear MCO2 source selection bits
    RCC_CFGR = (RCC_CFGR & ~(0x03 << RCC_CFGR_MCO1_SHIFT)) | ((src & 0x03) << RCC_CFGR_MCO1_SHIFT);
}

void rcc_mco1_set_prescaler(uint8_t prescaler)
{
    uint8_t v = 0;  // no division
    switch (v)
    {
        case 2:
            v = 0x04;   // division by 2
            break;
        case 3:
            v = 0x05;   // division by 3
            break;
        case 4:
            v = 0x06;   // division by 4
            break;
        case 5:
            v = 0x07;   // division by 5
            break;
        default:
            break;
    }
    RCC_CFGR = (RCC_CFGR & ~(0x07 << RCC_CFGR_MCO1PRE_SHIFT)) | ((v & 0x07) << RCC_CFGR_MCO1PRE_SHIFT);
}

void rcc_mco2_set_source(uint8_t src)
{
    // Clear MCO2 source selection bits
    RCC_CFGR = (RCC_CFGR & ~(0x03 << RCC_CFGR_MCO2_SHIFT)) | ((src & 0x03) << RCC_CFGR_MCO2_SHIFT);
}

void rcc_mco2_set_prescaler(uint8_t prescaler)
{
    uint8_t v = 0;  // no division
    switch (v)
    {
        case 2:
            v = 0x04;   // division by 2
            break;
        case 3:
            v = 0x05;   // division by 3
            break;
        case 4:
            v = 0x06;   // division by 4
            break;
        case 5:
            v = 0x07;   // division by 5
            break;
        default:
            break;
    }
    RCC_CFGR = (RCC_CFGR & ~(RCC_CFGR_MCO2PRE_MASK << RCC_CFGR_MCO2PRE_SHIFT)) | ((v & RCC_CFGR_MCO2PRE_MASK) << RCC_CFGR_MCO2PRE_SHIFT);
}