library ieee;
use ieee.std_logic_1164.all;
entity ff_t is
    port
    (t  : in std_logic;
     ck : in std_logic;
     set : in std_logic;
     rst : in std_logic;
     q, nq : buffer std_logic);
end ff_t;

architecture comportamental of ff_t is
begin
    process (ck, set, rst, t)
    begin
        if (rst='1') then q<='0'; nq<='1';
        elsif (set='1') then q<='1'; nq<='0';
        elsif (ck'event and ck='0') then
            if (t='1') then q <= not(q); nq <= not(nq);
            else q <= q; nq <= nq;
            end if;
        end if;
    end process;
end comportamental;