dc_comp2

 library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;



entity dc_comp2 is

  port

  ( d      : in std_logic_vector (3 downto 0);

    q      : out std_logic_vector (3 downto 0);

    sign   : out std_logic );

end dc_comp2;









ARCHITECTURE behv OF dc_comp2 IS

Signal  m   : std_logic_vector (15 downto 0);



BEGIN



  -- q <= "1110";

  -- sign <= '1';



  m(0)  <=(NOT d(3) AND NOT d(2) AND NOT d(1) AND NOT d(0));

  m(1)  <=(NOT d(3) AND NOT d(2) AND NOT d(1) AND     d(0));

  m(2)  <=(NOT d(3) AND NOT d(2) AND     d(1) AND NOT d(0));

  m(3)  <=(NOT d(3) AND NOT d(2) AND     d(1) AND     d(0));

  m(4)  <=(NOT d(3) AND     d(2) AND NOT d(1) AND NOT d(0));

  m(5)  <=(NOT d(3) AND     d(2) AND NOT d(1) AND     d(0));

  m(6)  <=(NOT d(3) AND     d(2) AND     d(1) AND NOT d(0));

  m(7)  <=(NOT d(3) AND     d(2) AND     d(1) AND     d(0));

  m(8)  <=(    d(3) AND NOT d(2) AND NOT d(1) AND NOT d(0));

  m(9)  <=(    d(3) AND NOT d(2) AND NOT d(1) AND     d(0));

  m(10) <=(    d(3) AND NOT d(2) AND     d(1) AND NOT d(0));

  m(11) <=(    d(3) AND NOT d(2) AND     d(1) AND     d(0));

  m(12) <=(    d(3) AND     d(2) AND NOT d(1) AND NOT d(0));

  m(13) <=(    d(3) AND     d(2) AND NOT d(1) AND     d(0));

  m(14) <=(    d(3) AND     d(2) AND     d(1) AND NOT d(0));

  m(15) <=(    d(3) AND     d(2) AND     d(1) AND     d(0));



  q(0)  <= m(1) OR m(3) OR m(5) OR m(7) OR m(9) OR m(11) OR m(13) OR m(15);

  q(1)  <= m(2) OR m(3) OR m(6) OR m(7) OR m(9) OR m(10) OR m(13) OR m(14);

  q(2)  <= m(4) OR m(5) OR m(6) OR m(7) OR m(9) OR m(10) OR m(11) OR m(12);

  q(3)  <= m(8);

  sign  <= m(8) OR m(9) OR  m(10) OR  m(11) OR  m(12) OR  m(13) OR  m(14) OR m(15);



END behv;