library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity SUM_main is
port (CLK : in std_logic;
      A : in std_logic_vector (3 downto 0);
      B : in std_logic;
      SUM : out std_logic_vector (3 downto 0)
  );
end SUM_main;

architecture behavioral of SUM_main is

component COUNT_main is
    Port ( CLK : in STD_LOGIC;
    C : inout STD_LOGIC_VECTOR (1 downto 0));
end component;

signal nexts, current: STD_LOGIC_VECTOR (3 downto 0);
signal Cin: STD_LOGIC;
signal C: STD_LOGIC_VECTOR (1 downto 0);

begin

mapping: COUNT_main PORT MAP (CLK=>CLK, C=>C);

process (CLK)
begin
if (rising_edge(clk)) then
    if B ='0' and Cin='0' then
        Cin <= '0';
        nexts <= current;
    elsif B='1' xor Cin='0' then
        Cin <= '0';
        nexts <= current+1;
    elsif B ='1' and Cin='1' then
        Cin <= '1';
        nexts <= current;
    end if;
 current <= nexts;   --state change.
end if;
end process;

process (C)
begin
    if C = "00" then
    current <= A;
    elsif C = "11" then
    SUM <= nexts;
end if;
end process;

end behavioral;